Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Rethinking AI Infrastructure: The Rise of PCIe Switches

Boring? Think Again. PCIe Switches Are the Hidden Power Behind AI When thinking of…

• 5 min read
controller IP , CXL , PCIe controller , Design IP , PCIe Gen4 , pcie4 , PCIe 7.0 , IP design , PCIe , future of IP , PCIe PHY , PCIe 6.0 , PCI Express

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Verification

Verification of PCIe's TDISP for Device Interface Security

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring…

• 5 min read
Verification IP , Functional Verification , CXL3.0 , PCIe , TDISP , IDE , verification

System, PCB, & Package Design 

BoardSurfers: Training Insights: Learn RF Design with Allegro X RF PCB Course

The Allegro®︎ X RF PCB course offers a practical, one-day training for engineers…

• 3 min read
RF PCB , Allegro X PCB Editor , BoardSurfers , PCB Editor , PCB design , Training Insights , allegro x

System, PCB, & Package Design 

Join Cadence Community Super User Program

Join the Community Super User Program to share expertise, inspire peers, and grow…

• 1 min read
PCB , community forum , PCB design , CADENCEFORUMS

Corporate News

ICSense Designs ASICs for Next-Generation Medical Implants

ICsense is a leading supplier of application-specific integrated circuits (ASICs…

• 2 min read
spectre simulation , Virtuoso Studio , Xcelium Logic Simulator , designed with cadence , Voltus

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

• 1 min read
IC25.1 , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement , IC Release Blog , Custom IC Design , Cadence Community

SoC and IP

Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

As AI data centers continue to scale up and out to accommodate increasingly compute…

• 1 min read
PCIe controller , ucie , HBM , PCIe 7.0 , PCIe , DDR IP , UALink , PCIe 6.0 , PCI Express

Digital Design

Enhancing RTL Power Efficiency with xReplay, FlashReplay, and Clock Gating

Innovative Solutions for Power-Efficient RTL Design and Technology As semiconductor…

• 6 min read
digital badge , Low Power , Power-Efficient Design , Joules , training , training bytes , Power Analysis , online training , clock gating , RTL analysis

Verification

An Overview of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful…

• 4 min read
CXL , Verification IP , VIP , PCIe , verification

Corporate News

3D-ICs in the Automotive Market: Breaking Barriers with AI-Driven EDA Tools

The automotive industry is experiencing a significant transformation as it adopts…

• 6 min read
Automotive , chip design , 3D-IC , automotive electronics , integrity 3d-ic , indesign , jedai , AI

Life at Cadence

Restoring Nature, One Vine at a Time

Written by Shrini Farrahi A dedicated team of 30 Cadence volunteers recently came…

• 1 min read
Cadence Giving Foundation , giving back , LifeAtCadence , We Are Cadence , volunteering , One Cadence One Team

System, PCB, & Package Design 

Case Study: How to Sign Off Your UCIe Interface

As 3D heterogeneous integration (3DHI) systems increase in complexity, the importance…

• 3 min read
IC Packaging , Signal Integrity , Sigrity , SystemSI

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Power Tradeoffs for Chiplets: What Designers Need to Know

The rise of chiplets in advanced system design presents opportunities as well as…

• 3 min read
chiplets , Voltus IC Power Integrity Solution , Power Integrity

Corporate News

Unlocking Breakthroughs with Accelerated Compute

The future of system and electronic design is here—and it’s unprecedentedly fast…

• 6 min read
Protium , Palladium , accelerated compute , millennium

Verification

Evolution of CXL PBR Switch in the CXL Fabric

Compute Express Link (CXL) is a transformative technology that significantly improves…

• 5 min read
Fabric manager , Routing , switch , CXL3.0 , CXL switch , TYPE , SPID , PBR , DPID

Life at Cadence

Shaping the Future Through Experience

This summer, Cadence hosted five interns in partnership with Break Through Tech at…

• 2 min read
STEM , Work that matters , LifeAtCadence

SoC and IP

CNNs and Transformers: Decoding the Titans of AI

In the rapidly advancing field of artificial intelligence, two neural network architectures…

• 8 min read
IP , ip cores , Tensilica , SSG , semiconductor IP , AI
CDNS - Fix Layout Hompage