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Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
Cadence Japan 8 Jan 2026 • less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
Corporate 6 Jan 2026 • 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
Cadence Japan 22 Dec 2025 • less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
KomalJohar 17 Dec 2025 • 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

  • All 6209
  • Corporate News 226
  • Life at Cadence 202
  • Academic Network 167
  • Analog/Custom Design 782
  • Artificial Intelligence 24
  • Cloud 21
  • Computational Fluid Dynamics 368
  • Data Center 41
  • Digital Design 442
  • Learning and Support 58
  • RF Engineering 115
  • SoC and IP 419
  • System, PCB, & Package Design  1000
  • Verification 1302
  • Cadence Japan 10

  • CFD(数値流体力学) 45
  • 中文技术专区 15
  • カスタムIC/ミックスシグナル 194
  • PCB、IC封装:设计与仿真分析 136
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  • RF /マイクロ波設計 45
  • Spotlight Taiwan 61
  • The India Circuit 92
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

カスタムIC/ミックスシグナル

Virtuosity: .simrc ファイルとネットリストのカスタマイズの裏側にある謎

ネットリスティングはデザインシミュレーションにおいて不可欠な部分です。ネットリストは、望ましいシミュレーション結果を達成するためにシミュレータにコネクティビティとマッピングの情報を伝えるために作成します…

Custom IC Japan 28 Jul 2021 • 1 min read
ic design methodology , AMS , Analog Design Environment , ic analog design , Cadence blogs , programming , mixed-signal simulators , custom/analog , Analog Simulation , analog , Mixed-Signal , full custom ic design , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , ICADVM20.1 , Circuit Design , mixed signal , analog design , japanese blog , Custom IC Design , IC6.1.8 , SKILL , Schematic , Analog IC Design , custom design technology , custom integrated circuit

Computational Fluid Dynamics

The CFD Vision 2030 Roadmap: 2020 Status, Progress, and Challenges

After a long writing (and longer editing and approval seeking) process, the AIAA…

John Chawner 28 Jul 2021 • 2 min read
CFD , Numerical Algorithms , geometry modeling , Knowledge Extraction , Multidisciplinary , Computational Fluid Dynamics , optimization , visualization , CFD Vision 2030 , HPC , Mesh Generation , simulation

Breakfast Bytes

July Update

This is the July edition of the now monthly update post, with small updates to existing…

Paul McLellan 28 Jul 2021 • 8 min read
ransomware , featured post , 6ghz , update , inmos , spectrum , GlobalFoundries , supply chain attack , newport wafer fab

Breakfast Bytes

Designed with Cadence Video Series

Designed with Cadence is a video series made with Cadence customers about how they…

Paul McLellan 27 Jul 2021 • 1 min read
featured post , video , designed with cadence , dwc

Breakfast Bytes

HOT CHIPS 2021 Preview

As usual in August, it is HOT CHIPS. I always find this one of the most interesting…

Paul McLellan 26 Jul 2021 • 4 min read
Intel , AMD , IBM , Samsung , hot chips , ARM

中文技术专区

6G时代来了,我们应该为设计准备什么?

7月22日至23日,为期两天的“电子设计创新大会(EDICON China 2021)”在上海博雅酒店成功举行,本次大会汇聚了业界一众技术专家与企业领袖,与大家共同探讨最前沿的技术与最新行业发展趋势…

FormerMember 26 Jul 2021 • less than a min read
5G , awr , RF design , Sigrity , Allegro , 6G , clarity

RF /マイクロ波設計

μWaveRiders:Cadence AWR Design Environment V16 ソフトウェアのリリースをハイライト

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

RF Design Japan 25 Jul 2021 • less than a min read
microwave , RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , japanese blog , awr v16 , AWR Design Environment release , Visual System Simulator(VSS)

Breakfast Bytes

Sunday Brunch Video for 25th July 2021

https://youtu.be/cwT7KL4iShY Made on "a tropical beach" Monday: Aerospace and Defense…

Paul McLellan 25 Jul 2021 • less than a min read
sunday brunch

RF Engineering

μWaveRiders: Cadence AWR Design Environment V16 Software Release Highlights

The Cadence AWR Design Environment V16 production release is now available for download…

TeamAWR 23 Jul 2021 • 3 min read
RF Simulation , Circuit simulation , Analyst 3D FEM EM Simulator , RF design , AXIEM 3D Planar Simulator , microwave office , Visual System Simulator (VSS) , awr v16 , AWR Design Environment release

Computational Fluid Dynamics

This Week in CFD

Given that I'm perpetually late on sharing This Week in CFD here on the Cadence CFD…

John Chawner 23 Jul 2021 • less than a min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Omnis

System, PCB, & Package Design 

BoardSurfers: Accelerating Allegro Layout Tools Using NVIDIA GPUs for Complex Board…

Boards and Packages are getting extremely complex and large; what used to be considered…

pbernard 23 Jul 2021 • 1 min read
Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Download Manager – Better than Ever Before

The Download Manager user interface has been revamped in 17.4-2019 HotFix 019. Various…

Shikha Jain 23 Jul 2021 • 3 min read
Cadence Design Systems , Installation Know-How , 17.4 , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , Download Manager , OrCAD , installation , Allegro

Computational Fluid Dynamics

Damen: Wind Study On A Slender Boat Design Using Computational Fluid Dynamics

DAMEN and Numeca develop a CFD methodology to proof a vessel has sufficient transversal…

AnneMarie CFD 23 Jul 2021 • 1 min read
naval archicture , Marine Engineering , Wind Study , fluid dynamics , IMO regulations , simulation software

Breakfast Bytes

Machine Learning in EDA

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design , I talked…

Paul McLellan 23 Jul 2021 • 5 min read
featured post , xcelium ml , cerebrus , JasperGold , allegro x

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.019 is Now Available

The HotFix 019 (QIR 3, indicated as 2021.1 in the application splash screens) update…

AllegroReleaseTeam 22 Jul 2021 • 6 min read
System Capture , 17.4 , OrCAD Capture , PSPICE , PCB Editor , EDM , Allegro Package Designer , 17.4-2019 , Topology Explorer , Allegro System Capture , Allegro PCB Editor , Pulse , 17.4-QIR3

Breakfast Bytes

Cadence Cerebrus - Intelligent Chip Explorer

This morning, we announced the Cadence Cerebrus Intelligent Chip Explorer, a machine…

Paul McLellan 22 Jul 2021 • 5 min read
Genus , featured post , cerebrus , cloud , cadence cloud , Innovus , digital full flow , physical design , Synthesis , timing signoff

Life at Cadence

How Culture Can Flourish in the New Normal

Peter Drucker rightly said, “Culture eats strategy for breakfast”. An inclusive high…

Jaswinder 21 Jul 2021 • 5 min read
Culture

Breakfast Bytes

CadenceLIVE Cloud Panel

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a…

Paul McLellan 21 Jul 2021 • 11 min read
featured post , on-prem , cloud , cadencelive americas , cadence cloud , cadencelive

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: Cadence Learning and SupportポータルのVirtuoso RF Solutionプロダクト…

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 20 Jul 2021 • 1 min read
VRF , Virtuoso Meets Maxwell , COS product page , Virtuoso RF Solution , Spectre , japanese blog , Clarity 3D Solver , Cadence Learning and Support portal , Custom IC Design , VMM
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