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Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

SoC and IP

From Spec to Silicon: Successful Physical AI System Chiplet Bring-Up

The semiconductor industry is advancing at an unprecedented pace, driven by the need…

• 7 min read
ucie , IP , chiplets , physical ai , lpddr5x , ARM , AI

Cloud

Worried About Security? Cadence OnCloud Has Your Back

Securing Innovation As chip design complexity and expectations increase, engineering…

• 1 min read
security , Managed Cloud , Secure Innovation , EDA , cloud , oncloud , cadence cloud , cloud eda

Corporate News

Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

• 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

System, PCB, & Package Design 

Optimization of IBIS-AMI Model Parameters with ML Algorithms

Serial link speeds have increased 25X in under 20 years, thus increasing the complexity…

• 2 min read
Serial link analysis , machine learning , optimization , Signal Integrity , Sigrity

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

• 1 min read
ChipStack , featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

Analog/Custom Design

Small-Signal Analyses Using HB and Shooting Newton Methods in SpectreRF Option

In the world of RF and analog design , understanding how circuits behave under periodic…

• 4 min read
blended , blended training , RF Simulation , Cadence blogs , learning , training , spectreRF , Cadence training , digital badges , training bytes , Virtuoso , Spectre , learning map , RF design , Custom IC Design , online training , Custom IC

Analog/Custom Design

Large-Signal Analyses Using HB and Shooting Newton Methods in SpectreRF Option

In the realm of RF and analog design , understanding how circuits behave under real…

• 4 min read
blended , blended training , RF Simulation , Cadence blogs , Spectre RF , learning , training , Cadence training , digital badges , training bytes , Virtuoso , Spectre , learning map , RF design , Custom IC Design , online training , Custom IC

Analog/Custom Design

Virtuoso Studio: Working in Comfort - New Display Theme and Readability Upgrades

The latest update to Virtuosos Studio brings a more refined, modern visual experience…

• 4 min read
Cadence blogs , Virtuoso Studio , Custom IC Design

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

• 3 min read
ucie , xcellium , IP , featured , PHY , Palladium , PCIe , neoverse , DDR , ARM

Verification

Don’t Let Constraint Random Verification Become Your Nightmare!

Use a graphical view to help with debugging by harnessing visual tools to demystify…

• 6 min read
SystemVerilog , uvm , debug , Functional Verification , random , Verisium Debug , constraint , verification

Analog/Custom Design

New Spectre AMS Designer Features in XCELIUM 25.09

The Spectre AMS Designer features are now available through the XCELIUM 25.09 release…

• 1 min read
S-parameter Analysis , 25.09 , AMS-Designer , AMS in ADE , AMS Designer , AMSD , Spectre AMS Designer , inverse logic option , XDP , Custom IC Design , XCELIUM 25.09

Digital Design

Lights, Camera, Subtitles! Genus Training Just Got a Mandarin Makeover

Imagine, you're binge-watching your favorite web series. The plot is gripping, the…

• 4 min read
Genus , online courses , Mandarin , Genus Synthesis Solution , online training

Analog/Custom Design

Place-Like Layout Schematic for Photonics Feature A New Era in Photonic Design

In photonic integrated circuit (PIC) design, the Mach-Zehnder Interferometer (MZI…

• 3 min read
quantum computing , Virtuoso Schematic Editor , Cadence blogs , Virtuoso Studio , PIC , AMS Designer , Rapid Adoption Kit , analog , Virtuoso RF , Layout EXL , Photonics Summit , Cadence training , Virtuoso , Analog Design Environment , RF design , photonics , mixed signalsignals , Circuit Design , online training , Custom IC

Cloud

True Hybrid Cloud Skyrockets Innovation

Unlocking the Power of True Hybrid Cloud for EDA Workloads As electronic design automation…

• 1 min read
Managed Cloud , True Hybrid Cloud , EDA , cloud , Lift and Shift , cadence cloud , cloud eda

Verification

PCIe Low-Power Validation Challenges and Potential Solutions (PIPE/L1 Substates)

As chip complexities increase and the industry evolved to more battery-powered devices…

• 3 min read
Verification IP , Low Power , PCIe , verification

Digital Design

Accelerating Silicon Success with Cadence’s Digital Full Flow

Cadence's Digital Full Flow delivers RTL-to-GDSII convergence with industry-leading…

• 1 min read
training , Cadence Cerebrus Intelligent Chip Explorer , digital full flow

SoC and IP

Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Modern compute systems have evolved beyond reliance on a single dominant interface…

• 2 min read
Design IP , PHY , AI Inferencing , 25G Ethernet , Edge Computing , 10G-KR , PCIe 5.0 , Ethernet , PCIe , SerDes , SerDes IP , Concurrent Multi-protocol Support , Multi-link , multi-protocol , AI

System, PCB, & Package Design 

BoardSurfers: Training Insights: Automating Artwork Configuration in PCB Editor

The Artwork Configuration feature of Allegro X PCB Editor in Release 24.1 automates…

• 3 min read
PCB Design Automation , Gerber file creation , PCB Editor Workflow , Allegro X PCB Editor , artwork , Automating PCB Artwork , Allegro PCB Editor , artwork film workflow , artwork film generation , Cadence Allegro Training , Film Generation in PCB , Allegro , film setup in Allegro X

Life at Cadence

Empowering the Next Generation of Engineers: UKESF Student Bursary Event 2025

Electronics lies at the heart of today's technological revolution, fuelling innovation…

• 3 min read
STEM , Cadence UK , Cadence Cares , giving back , volunteer
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