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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

Programming Persistent Memory

I talked earlier this week about the recent persistent memory summit (see my post…

• 5 min read
programming model , persistent memory

Analog/Custom Design

Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

An important requirement for project sign-off is to ensure that all the design simulations…

• 2 min read
verifier , PVT , coverage , Analog Coverage , Analog Simulation , Virtuoso Analog Design Environment , space , Custom IC Design , Assembler , verification

Breakfast Bytes

Persistent Memory

Last week was the latest Persistent Memory Summit. In the semiconductor world, we…

• 8 min read
persistence , Intel , non-volatile , persistent memory summit , ReRAM , optane , MRAM , persistent memory , 3dxpoint

Breakfast Bytes

What Next for Modus DFT?

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the…

• 3 min read
modus , Test , scantest

Verification

Specman is Sweet – Bosch Sensortec's Story

Recently, Bosch Sensortec has been using Specman for their functional verification…

• 1 min read
Specman , Bosch , e , success

Breakfast Bytes

CES: 5G, All Hat and No Cattle

Increasingly, CES seems to be less about consumer electronics, and more about the…

• 9 min read
5G , mmwave , CES , MWC

Analog/Custom Design

Virtuosity: Introducing the Pin Tool

The Pin Tool follows an object-based approach to working with pins by consolidating…

• 2 min read

Life at Cadence

Empowered to Support Our Community

Cadence understands that the success of our business, our employees, and the community…

FormerMember • 2 min read
Insights on Culture , giving back , Fortune 100 best companies to work for , great place to work

Verification

New Training Bytes Available Now: All About SystemVerilog Classes

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking…

• 2 min read
SystemVerilog , Functional Verification , classes , training , training bytes

Breakfast Bytes

IEDM: Embedded Memories

On the Sunday of IEDM are two short courses, one memory-focused, and one logic-focused…

• 6 min read
Memory , deep learning , eflash , flash , envm , RRAM , MRAM , PCRAM , edram

Breakfast Bytes

Sunday Brunch Video for 27th January 2019

https://youtu.be/1gxIy7TGg3c Made at EBC (camera Sean) Tuesday: DesignCon: The Integrity…

• less than a min read
DesignCon , bletchley park , Amazon , gsa , dan niles

PCB、IC封装：设计与仿真分析

Cadence Sigrity 邀您莅临DesignCon 2019

时间：1月29-31日 地点：Santa Clara Convention Center，美国加州 Cadence诚邀您莅临DesignCon #711 展台，了解如何利用Cadence…

• less than a min read
SI , PI , Chinese blog , 电源完整性 , DesignCon , Multi-Gigabit , IC封装设计 , 光电设计 , 高级封装 , IBIS-AMI , 中文 , SerDes , DDR , Sigrity , 信号完整性

Breakfast Bytes

Amazon Go: Just Walk Out Shopping

Last year you probably heard about Amazon Go when it opened in Seattle. This is a…

• 3 min read
amazon go , mobile , Amazon , whole foods

Analog/Custom Design

Spectre Tech Tips: Optimizing Spectre APS Performance

This blog discusses how to optimize the Spectre APS performance for analog and mixed…

• 14 min read
spectre aps , Circuit simulation , ADE Explorer , simulation performance , Simulation Accuracy , Spectre XPS MS , ADE , Spectre Tech Tips , Spectre

Breakfast Bytes

"The First Half of 2019 Is Likely to Be Really Bad"

The title of this post was the single line summary of Dan Niles' quarterly outlook…

• 5 min read
capex , niles , Semiconductor , mobile , gsa

Breakfast Bytes

Why the Nation That Invented the Computer Lost Its Lead

Last month I wrote about a piece that Lynn Conway wrote for IEEE Computer Magazine…

• 9 min read
colossus , bletchley

Breakfast Bytes

DesignCon: The Integrity Show

It's the end of January and that means DesignCon. It is January 29th to 31st in the…

• 3 min read
PCB , DesignCon , Power Integrity , silicon photonics , Signal Integrity , photonics , Sigrity

The India Circuit

A Boost For Fabless Chip Design in India

There was a lot of excitement when the National Policy on Electronics was announced…

• 3 min read
National Policy on Electronics , entrepreneurship , Electropreneur Park , SFAL , FabCi , ESDM , npe

Breakfast Bytes

Sunday Brunch Video for 20th January 2019

https://youtu.be/Bs5A09med6Q Made at the Cadence campus in the rain (camera Sean…

• less than a min read
alphazero , CES , AMD , Tensilica , EUV , IEDM
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