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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Computational Fluid Dynamics

Meet Our Marine CFD Experts at the Euromaritime Exhibition

On June 28-30 2022, the Maritime Community meets again in Marseille at this biennial…

• 1 min read
CFD , naval archicture , Marine Engineering , marine , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , naval

Breakfast Bytes

Secure Before You Fabricate

One thing that I have come into contact with recently is the notion that the US defense…

• 5 min read
security , Mil-Aero , prototyping , Protium , Palladium , Emulation

Verification

Device Training for High Speed DRAMs

As the device frequencies and the data rates go up with every new generation of Interface…

• 3 min read
Verification IP , ddr5 , VIP , JEDEC , Training Modes , lpddr5 , lpddr5x , memory models , DDR5DIMM

Breakfast Bytes

The Convergence of Photonic and Electronic ICs

At the recent DesignCon in Santa Clara, one of the keynotes was by John Bowers of…

• 4 min read
DesignCon , silicon photonics , photonics

Spotlight Taiwan

Cadence Perspec驗證在異質多核心行動處理器之應用

作者:Vic Chen, Principal Application Engineer, Cadence可攜式測試與刺激標準(Portable Test and…

• 1 min read
PSS Methodology , Perspec , cadencelive taiwan , perspec system verifier , taiwanese blog

Breakfast Bytes

Sunday Brunch Video for 10th April 2022

https://youtu.be/fmV1XVY-ZiI Made at Coyote Hills Regional Park (camera Carey) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro PCB Ed…

The HotFix SPB17.40.028 of 17.4-2019 of Allegro® PCB Editor has been rolled out and…

• 3 min read
17.4 , BoardSurfers , padstack , DesignTrue DFM , QIR4 , 17.4-2019 , Constraints , Allegro PCB Editor , Allegro

Breakfast Bytes

Ericsson Cellular Network at TÜV Rheinland Test Center

At the end of March, I went to the TÜV Rheinland Test Center. TÜV stands for Technischer…

• 4 min read
Automotive , Ericsson , tüv , mobile

Breakfast Bytes

Identity Is the New Perimeter

On March 10th, Black Hat organized a webinar called Identity is the New Perimeter…

• 9 min read
security , black hat , orange

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 13: Analog Fault S…

While the analog and mixed-signal components are the leading source of test escapes…

• 4 min read
Automotive , legato , ICADVM20 , functional safety , analog fault simulation , analog , training bytes , Virtuoso , Analog IC Design videos , Spectre , 1 , Virtuoso Video Diary , aging , Custom IC Design , IC6.1.8 , reliability , Legato Reliability , ADE Assembler

PCB設計／ICパッケージ設計

2022年3月リリース、Cadence OrCAD / Allegro17.4-2019 HotFix SPB17.40.028の新機能ハイライト

OrCAD® および Allegro®のHotFix 028 (QIR 4, アプリケーションのスプラッシュ画面で は “2022” と表示されます) の更新プログラムが…

• less than a min read
17.4 , PCB Editor , 17.4-2019 , OrCAD , Allegro System Capture , japanese blog , Allegro PCB Editor , Pulse , Allegro

Breakfast Bytes

Sam Zeloof: Who Needs a Cleanroom When You Have a Garage?

At the end of last year, I was mindlessly looking at YouTube when their "algorithm…

• 3 min read
sam zeloof , garage

Computational Fluid Dynamics

Replicating da Vinci’s Aerial Vehicle Design

The increasing value of the drone industry is pushing the limits of evaluating and…

• 3 min read
vehicle design , Unmanned Aerial Vehicles , UAV , da Vinci , CFD Applications , engineering , extreme maneuvers , drones , simulation , Aerodynamics

Computational Fluid Dynamics

Rank-N Nonlinear Harmonic Method Unlocks More Precise And Reliable Turbomachinery…

The NLH Rank-n feature unlocks the possibility of simulating unsteady phenomena across…

• 1 min read
CFD , turbomachinery , webinars , Computational Fluid Dynamics , fluid dynamics , nonlinear harmonic , CFD Applications , simulation software , rank-n , nlh , Turbo , simulation

Breakfast Bytes

Jack Dongarra Receives Turing Award

Last week, the ACM announced that Jack Dongarra was being honored with the 2021 Turing…

• 4 min read
turing award , supercomputer

SoC and IP

TWS Earbud Design: Scaling up

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier…

• 9 min read
Tensilica DSPs , Tensilica

SoC and IP

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

• 5 min read
featured , Tensilica

Verification

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

• 6 min read

Breakfast Bytes

Intelligent System Analog Design

There are many perceptions about analog design that might have been true once. For…

• 6 min read
analog , Virtuoso , mixed signal , Virtuoso Layout Suite EXL
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