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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
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Blog - Post List
Latest blogs

Breakfast Bytes

A Year of Breakfasts 2021

This year's Breakfast Bytes annual is out. It is titled A Year of Breakfasts 2021…

• 1 min read
a year of breakfasts 2021 , breakfast bytes book , Breakfast Bytes

Computational Fluid Dynamics

Pointwise V18.4 R4 Now Available for Download and Production Use

As the title says, Pointwise Version 18.4 R4 is now available for download and production…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , Mesh Generation , Meshing

Analog/Custom Design

Start Your Engines: Modeling Current-Based Port Connections between Electrical and…

In a mixed-signal simulation, the electrical signal modules and real number modeling…

• 5 min read
R2E conversion , real number modeling , AMS , AMS Designer , Start Your Engines , E2R , Mixed-Signal , mixed-signal verification

Breakfast Bytes

TSMC: Advanced Technology for Smartphone and HPC Platforms

Yujun Li, TSMC's director of business development for high-performance computing…

• 3 min read
5G , n5 , n5hpc , n3 , TSMC , HPC , n7 , n7hpc

定制IC芯片设计

Virtuoso Meets Maxwell: 从系统的角度思考—— 行业领先的IC与IC封装设计/验证工具间互操作性的优势

当下大多数的模拟，射频和混合信号设计都要求在不同衬底工艺上集成多颗IC，以达到所需的性能。异构元件集成方法可以帮助设计师实现单片SoC不容易实现的设计结果。与此同时…

• less than a min read
Chinese blog , IC Packaging , Virtuoso Meets Maxwell , Virtuoso RF Solution , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Spectre , Allegro

System, PCB, & Package Design 

BoardSurfers: Voiding Text in Copper Shapes

Almost every PCB design includes different types of shapes, mainly for ground and…

• 3 min read
PCB , 17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

CEO Outlook: "Let's Take Advantage of Our Industry Being in the Spotlight"

The Electronic System Design Alliance CEO Outlook took place on May 16. Bob Smith…

• 13 min read
ESDA , semi , ceo outlook , esd alliance

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Clarity 3Dソルバーでのシミュレーション用にポートを設定する

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso Meets Maxwell , Virtuoso RF Solution , Electromagnetic analysis , ICADVM20.1 , japanese blog , Clarity 3D Solver , Custom IC Design , Virtuoso Layout Suite EXL

Verification

AMBA 5 ACE/AXI Specification Updates and Their Support in Cadence ACE/AXI VIP

As discussed in the previous blog, the AMBA® 5 specification updates introduced several…

• 3 min read
amba5 , ACE5 , AXI5 , Funcional Verification , AMBA Verification IP , System Verification Scoreboard

System, PCB, & Package Design 

CFD: It's More Than an Acronym - Learn More at CadenceLIVE

Excuse me, sir. Are you lost? That's what you might be thinking. Why is this guy…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , NUMECA

Breakfast Bytes

Countdown to TSMC Technology Symposium: 7nm, 5nm, 3nm, June 1

Today it is the TSMC 2021 Online North America Technology Symposium (tomorrow for…

• 3 min read
n4 , n3 , TSMC , TSMC Technology Symposium , custom/analog flow , digital full flow

Analog/Custom Design

Virtuoso Meets Maxwell: Defining Ports in EMX Planar 3D Solver

Fast and accurate electromagnetic simulation is becoming critical in a growing number…

• 6 min read
VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , EMX , EM Analyis , RF design , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL

PCB、IC封装：设计与仿真分析

如何在IC封装设计中告别锐角问题？

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年…

• less than a min read
PCB , IC , Chinese blog , 17.4 , APD , Allegro Package Designer Plus , PCB设计 , 中文 , IC封装 , 锐角 , Allegro

Digital Design

Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

In the concluding blog of our "Demystifying ESD" series, we walk you through the…

• 6 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , ESD reports , electrostatic discharge , current density , Power Integrity , Innovus , clamp , bump

Digital Design

SSV 21.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download…

• 3 min read
Celsius Thermal Solver , Temperature Map , Voltus IC Power Integrity Solution , 3nm , Power Integrity , Power Targets , silicon signoff , Tempus Timing Signoff Solution , Extreme Modeling

Breakfast Bytes

Offtopic: "Pole Pole" to the Top of Kilimanjaro

Today is the last blogging day before Memorial Day on Monday, so as is now traditional…

• 8 min read
offtopic

Computational Fluid Dynamics

Fluid Dynamics Investigation of the Sonic Boom on a Supersonic Aircraft

The return to supersonic flight is amongst the hottest topics in aviation today,…

• 1 min read
CFD , Aerospace , Computational Fluid Dynamics , fluid dynamics , NUMECA , Omnis

Breakfast Bytes

Why Attend CadenceLIVE Americas 2021 on June 8 and 9?

Once again this year, CadenceLIVE Americas is coming up soon and it will be completely…

• 6 min read
cadencelive americas , cadencelive

Analog/Custom Design

Virtuosity: Learn the Right Steps—Design 5G Your Way with Cadence Training

In this blog we would like to let you know – amongst other things - how to implement…

• 3 min read
5G , Virtuoso RF , training , Cadence training , digital badges , Virtuoso , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training
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