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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

定制IC芯片设计

技术性：器件的自动布局和布线 — 基于行的器件放置

Device-level automatic placer允许您以约束和网格兼容的方式放置器件和设备组. 您可以使用交互式设备放置选项半自动放置设备.

• less than a min read
Chinese blog , Automatic Placement , Virtuoso Placer , Auto P&R , Virtuosity , Virtuoso Placement , Custom IC Design

Breakfast Bytes

Sunday Brunch Video for 19th January 2020

https://youtu.be/O90mUZyWIeE Made at Lick Observatory (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

Off-Topic: Picas, Points, and Printing

Monday is Martin Luther King, Jr Day, and Cadence will be off. Breakfast Bytes will…

• 7 min read
offtopic , printing

定制IC芯片设计

Virtuoso视频日记：简单的方法来解决 复杂的问题——schTraceNet

基于SKILL函数 schTraceNet 定义一个回调函数，将被探测的信号带入到下一层，这样就可以解决层次化原理图设计中遇到的复杂问题。

• less than a min read
schTraceNet , Chinese blog , Virtuoso Schematic Editor , ICADVM18.1 , Net Tracing , video , tracing a net , Virtuoso , Schematic Editor , Virtuoso Video Diary , Probing , Circuit Design , Probes assistant , Custom IC Design , Custom IC , IC6.1.8 , Schematic , net area

Breakfast Bytes

Emerging Memory

SNIA, the Storage Networking Industry Association, organized a webinar recently with…

• 5 min read
Memory , optane , MRAM , persistent memory , 3dxpoint

The India Circuit

Of Brains and Computers: Keynote by Dr Jan Rabaey

One of the industry’s biggest events, the VLSI Design Conference, took place in Bangalore…

• 3 min read
janrabaey , VLSID2020 , BWRC

Breakfast Bytes

5G in 2020

There is a famous quote, attributed to Mark Twain but more likely said by his friend…

• 6 min read
5G , CES , ces2020

System, PCB, & Package Design 

BoardSurfers: DFF - Three Steps to Perfect Mask Defined Padstacks in Your PCB

We will of course not venture into the finer points of the debate about mask-defined…

• 3 min read
PCB Editor

System, PCB, & Package Design 

IC Packagers: The Default Bond Wire Profile - PROFILE1 (And Three Reasons Why Not…

For those of you who do wire-bond package substrate – whether you’re designing a…

• 6 min read
Allegro Package Designer

Breakfast Bytes

Mark Cuban on Media and AI

At CES there was a session in which Mark Cuban was interviewed. As he pointed out…

• 4 min read
CES , ces2020 , AI

定制IC芯片设计

Virtuosity: 针对高阶工艺节点的器件级布线工具— 树型布线流程

本博客是Virtuoso器件级布线系列博客的最终篇，将介绍树干和树枝形成树的完整过程，通过这种类比方式，便于用户全面了解Tree Route 的流程及其功能. …

• 1 min read
Chinese blog , tree routing , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

Details of TSMC's IEDM Presentation on N5

At IEDM in December, one of the papers in the very last session (a sneaky trick to…

• 5 min read
n5 , TSMC , 5nm , IEDM

Breakfast Bytes

Sunday Brunch Video for 12th January 2020

https://youtu.be/y62D4tVK-_k Made at CES 2020 (camera Gerard Andrews) Last Thursday…

• less than a min read
sunday brunch

Breakfast Bytes

The Rosetta Stone and the British Museum

In the first week of January, I wrote about Lars Liebmann's Rosetta Stone of Lithography…

• 4 min read
british museum , sir john soane's museum , rosetta stone , museums

Breakfast Bytes

What's New in Consumer Electronics? CES 2020

I come to Las Vegas in the first week of January each year to attend what used to…

• 5 min read
5G , Automotive , CES , ces2020 , robotics , drones , AI

Breakfast Bytes

The 40th Anniversary of LAMBDA Magazine

Forty years ago today, January 8, 1980, the first issue of LAMBDA magazine was published…

• 8 min read
vlsi technology , lambda magazine , mead and conway

System, PCB, & Package Design 

IC Packagers: Four Reasons to Avoid Multi-Layer Flip-Chip Pin Padstacks

Designing a package substrate, there are things that many of us do that perhaps we…

• 5 min read
Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: PCB Electronics—Six Tasks to Prepare Board for Manufacturing

You have placed components and routed the board. You are finally ready to send the…

• 5 min read
PCB Editor

Breakfast Bytes

Open Source in 2020

I recently wrote a couple of posts about open-source EDA tools, OpenROAD: Open-Source…

• 9 min read
open source eda , open source
CDNS - Fix Layout Hompage