Explore the Cadence Community Forums to find and exchange in-depth technical information.

Featured

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Voltus Voice: A New Blog Series to Discover the “Power” Within

Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies…

• 3 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , video , Power Integrity , training , Voltus , Digital Implementation , Power Sigonff , design closure , IR drop , RAKs , EMIR

Digital Design

Library Characterization Tidbits: Did Your Search for Constraints Fail?

While using the Cadence Liberate Characterization solution or the Liberate Variety…

• 4 min read
search bound , Liberate Variety , library characterization , glitch metric , Library Characterization Tidbit , Digital Implementation , final state threshold , troubleshooting , Liberate , Constraints , Liberate Characterization Portfolio , glitch tolerance

カスタムIC／ミックスシグナル

Start Your Engines: UNLでアナログ・ブロックにSpectreネットリストを生成する理由と方法

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , Mixed Signal Verification , Unified Netlister , mixed signal , japanese blog , analog/mixed signal , AMS UNL

Breakfast Bytes

Yesterday Was Tau Day

You probably know that 3/14 is Pi Day, since pi (π) starts 3.14 and so matches the…

• 5 min read
PI , tau day , tau

Verification

Improving Tests Efficiency Using Coverage Callback (part 2)

In recent blogs - specman-callback-coverage-api and improving-tests-efficiency-using…

• 3 min read
Specman , Functional Verification , Coverage-Driven Verification , e , e language

Breakfast Bytes

Sunday Brunch Video for 28th June 2020

https://youtu.be/va13w0mgAco Made "under the sea" (camera Carey Guo) Monday: Make…

• less than a min read
sunday brunch

Digital Design

Curious About the Newly Released Innovus Implementation System v20.1?

We recently released the Innovus v20.1 software and you might be interested in learning…

• less than a min read
Digital Implementation , Innovus , Floorplanning and Prototyping

System, PCB, & Package Design 

BoardSurfers: Allegro In-Design Return Path Analysis: Find and Visualize Return Path…

Return path issues are common and difficult to diagnose in complex printed circuit…

• 2 min read
PCB SI , PCB design , Allegro

Life at Cadence

My Life at Cadence Video Series: Komal Gujarathi

Cadence recently interviewed five of our amazing women engineers for a new video…

• less than a min read
inclusion , Culture , STEM , cadence , my life at cadence , women

Breakfast Bytes

Cornami and Trusted Data

Recently, I wrote about Fully Homomorphic Encryption (FHE from now on) which I think…

• 7 min read
fhe , Wally Rhines , fully homomorphic encryption , cornami

Academic Network

Digital Design and Signoff Training Deep Dive: Part 3 – Silicon and Signoff Veri…

We’re excited to share the last blog for the Digital Design and Signoff Training…

• 3 min read
Europractice , Digital Design and Signoff , Cadence Academic Network , CMC Microsystems , online training , university program

カスタムIC／ミックスシグナル

Start Your Engines: AMSD Flex – 最新のSpectreの機能にすぐにアクセスできます！

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
mixed signal design , AMS Designer , AMSD , Mixed Signal Verification , AMSD Flex Mode , japanese blog

Breakfast Bytes

Under the Hood of Genus

From time to time people ask how EDA tools work under the hood. I think the question…

• 8 min read
Genus , featured , computational software , Synthesis , Placement

定制IC芯片设计

Virtuosity：您的版图设计是否结构正确 ？

您的设计是否结构正确？阅读此博客，以了解在设计过程中，如何使用宽度间距模式（WSPs），实现结构正确的设计。 WSPs 的追踪线，为快速创建连接线提供指导。定义WSPs以捕获宽度和间距规则…

• less than a min read
Chinese blog , ICADVM18.1 , Advanced Node , Layout Suite , width spacing patterns , Layout , Virtuoso , Virtuosity , usability , Custom IC Design , Custom IC , ux

System, PCB, & Package Design 

IC Packagers: How to Fix Padstacks that Aren’t Showing All Their Layers

We talked a few months ago regarding why flip-chip padstacks are single layer pads…

• 2 min read
Allegro Package Designer

Breakfast Bytes

Computational Digital Software

Cadence has been using the term "computational software" to unify many of the algorithms…

• 6 min read
Genus , ml , Tempus , computational software , machine learning , Innovus , digital full flow

Breakfast Bytes

vManager: One Manager to Rule Them All

Here's a high-level view of verification: If everyone properly plans their verification…

• 5 min read
featured , formal , Protium , Palladium , xcelium , JasperGold , simulation , vManager

Analog/Custom Design

Virtuoso Meets Maxwell: Full CellView EM Extraction

This blog introduces the full cellview extraction feature of the Virtuoso RF Solution…

• 7 min read
AXIEM , ICADVM18.1 , VLS EXL , EM Silimation , Virtuoso Layout EXL , Virtuoso RF Solution , Virtuoso , Custom IC Design

定制IC芯片设计

Virtuoso Meets Maxwell： 了解您的举动–我们正在进行芯片、封装和电路板协同编辑

该博客介绍了Cadence Virtuoso RF 解决方案中的Edit-in- Concert 技术，它可以帮助设计师们查看和编辑die packages 及其相应的die…

• less than a min read
Chinese blog , Edit-in-Concert , Virtuoso Meets Maxwell , Advanced Node , Virtuoso RF , Virtuoso , Custom IC Design
CDNS - Fix Layout Hompage