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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

Cadence OrCAD and Allegro 22.1 is Now Available

The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads . This…

• 6 min read
TopXp , Cadence Design Systems , Sigrity Aurora , PSpiceA/D , 22.1 , PSPICE , Topology Explorer , PCB design , Allegro System Capture , Allegro PCB Editor , Pulse , Allegro

Life at Cadence

IQM Is Building the Next Generation of Quantum Computers

IQM seeks to solve one of the greatest technological challenges globally: building…

• 1 min read
RF , awr , designed with cadence

Life at Cadence

RISC-V Is Thriving – Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley…

• 4 min read
risc-v

Breakfast Bytes

Latinx Heritage Month

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage…

• 2 min read
latinx , latinx heritage month , Hispanic

Analog/Custom Design

Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Design Capture and Packaging (DCP) utility lets you isolate, capture and package…

• 5 min read
mixed signal design , AMS Designer , AMSD , Start Your Engines , Mixed-Signal , Design Capture , Cadence Community

Digital Design

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

• 3 min read
Stratus HLS , Genus

Computational Fluid Dynamics

Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level…

• 4 min read
openeye scientific , molecular sciences , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Cadence CFD , drug delivery mechanism

カスタムIC／ミックスシグナル

Spectre Tech Tips: ダイナミック電流密度チェック

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります…

• 1 min read
spectre aps , Spectre 21.1 , Dynamic Checks , Dynamic design checks , Spectre Circuit Simulator , Spectre , japanese blog , spectre x

Verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Computational Fluid Dynamics

Last Week at Fidelity CFD

It's Monday and time to look back on what happened last week here at Cadence Fidelity…

• 3 min read
CFD , turbomachinery , webinars , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Mesh Generation

Computational Fluid Dynamics

On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor…

• less than a min read
CFD , Automotive , external aerodynamics , automotive engineering , featured , Computational Fluid Dynamics , fluid dynamics , simulation software , Aerodynamics

Digital Design

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

• 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Life at Cadence

Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Understand the role that density and compact design optimization play when designing…

• 5 min read
F1 , optimization , density , formula 1

Breakfast Bytes

USB-C – The Least Standard Standard Ever

In a post in our verification blog , Neelabh Singh told us that USB4 Version 2.0…

• 3 min read
usb 4.0 , USB , USB-C

Verification

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

Breakfast Bytes

HOT CHIPS: Arm's Morello

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some…

• 5 min read
morello , hot chips , ARM , cheri , capability

System, PCB, & Package Design 

Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Desi…

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering…

• less than a min read
SI , PI , IC , SSN anlysis , IC Packaging , Sigrity XcitePI , Co-Analysis , Power Integrity , CadenceLIVE China , Advanced-IC Package design , silicon interposer , Signal Integrity , 2.5D HBM , cadencelive , Sigrity SystemSI , Clarity 3D Solver , simulation

Verification

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

• 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Breakfast Bytes

CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so…

• 3 min read
RF , SiP , ship , ship-rf , 3dhi
CDNS - Fix Layout Hompage