Cadence Blogs

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 17 Oct 2022 • 4 min read

Verification IP , VIP , PCIe , pcie gen6 , verification

Computational Fluid Dynamics

Streamline Reading and Writing Files from Fidelity Pointwise

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was…

Veena Parthan 16 Oct 2022 • 6 min read

Meshing Monday , geometry cleanup , Computational Fluid Dynamics , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 14 Oct 2022 • 4 min read

Verification IP , PCIe , pcie gen6 , verification

System, PCB, & Package Design

System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis…

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify…

deeptik 14 Oct 2022 • 8 min read

IDA , Sigrity Aurora , Sigrity Topology Explorer , Power Integrity , SI/PI Analysis , Allegro Package Designer , Signal Integrity , PCB design , Clarity 3D Solver

Samsung Foundry Roadmap 2022

Recenty, it was the Samsung Foundry Forum (SFF). In fact, there was a pre-event for…

Paul McLellan 14 Oct 2022 • 4 min read

Samsung , samsung foundry , samsung foundry forum , sff , safe

Computational Fluid Dynamics

Fidelity Pointwise 2022.1 Hot Fix 2 Now Available

Fidelity Pointwise 2022.1 Hot Fix 2 is now available for download and production…

AnneMarie CFD 14 Oct 2022 • 1 min read

featured , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation , Meshing

Academic Network

Shift-Left Methodology for the Development of Hardware Accelerators Education Kit…

In order to describe the purpose of this education kit , let’s leave the EDA turf…

Anton Klotz 13 Oct 2022 • 3 min read

virtual prototyping , featured , Education Kit , Tensilica , Stratus , SystemC , high level synthesis , helium

Hassle-Free Rigid-Flex PCB Bending EM Analysis

The functionality, safety, and effectiveness of devices using rigid-flex PCBs are…

Ben Gu 13 Oct 2022 • 4 min read

rigidflex , electromagnetic

Butterfly Network Puts Ultrasound on a Chip with Cadence

About two-thirds of the world’s population lacks access to medical imaging, whether…

Corporate 13 Oct 2022 • 1 min read

featured , designed with cadence , vision , butterfly network

2022 Kaufman Award Honors Giovanni De Micheli

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of…

Paul McLellan 13 Oct 2022 • 5 min read

Kaufman Award , CEDA , IEEE , kaufman hall of fame , esd alliance

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

xinmu 12 Oct 2022 • 6 min read

Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification

Analog/Custom Design

Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for…

Virtuoso Release Team 12 Oct 2022 • 2 min read

Analog Design Environment , Cadence blogs , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , ICADVM20.1 , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Importance of MDIO Interface for Ethernet.

M edia I ndependent I nterface M anagement ( MIIM ), or M anagement D ata I nput…

AyushK 12 Oct 2022 • 1 min read

Verification IP , uvm , SoC verification , IP verification , Ethernet VIP , Functional Verification , Cadence VIP portfolio , MDIO Interface , Ethernet

How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

The chip design industry is going through exciting times. Process nodes with smaller…

Vinod Khera 12 Oct 2022 • 5 min read

advanced process nodes , Genus Synthesis Solution , Innovus Implementation

Digital Design

Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe…

Are you passionate about cooking? Err... Don't think it is a regular cooking class…

Neha Joshi 12 Oct 2022 • 1 min read

Low Power , Genus , IEEE 1801 , UPF , Synthesis

TSMC OIP Preview 2022

I have pointed out before that you really only get two opportunities a year to get…

Paul McLellan 12 Oct 2022 • 2 min read

OIP , TSMC

Cadence Certus Closure Solution: Automated Full-Chip Optimization

Today, we announced the Cadence Certus Closure Solution, the first-of-its-kind fully…

Paul McLellan 11 Oct 2022 • 2 min read

featured , Tempus , tempus eco , STA , static timing , certus