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System, PCB, & Package Design : ASCENT: Reusing Designs in Allegro System Capture

Rachna2018

This post is for those of you who have been creating logical designs and boards for a while. In most cases, a new product or design doesn’t require every component or module to be made from scratch. Most standard components are reused and, at t...
- 6 Jul 2021
RF /マイクロ波設計: 『コネクテッドカーを駆動する RF/マイクロ波技術』の翻訳版のご案内

RF Design Japan

先日、ご紹介した『コネクテッドカーを駆動する RF/マイクロ波技術』の翻訳版がダウンロードできるようになりました。ご興味頂いた方はぜひ資料をご参照頂き、弊社製品がコネクテッドカーの開発にどのように活用されているかご確認下さい。翻訳版は、ここからダウンロード可能です。 Author: Tsutomu Sugawara 関連するリソースホワイトペーパー RF/Microwave Technology Driving the Connected Car(English) コネクテッドカーを駆動...
- 6 Jul 2021
Breakfast Bytes: Sunday Brunch Video for 4th July 2021

Paul McLellan

https://youtu.be/Zb8vh-JjTQk Made in Long Ridge Open Space Preserve (camera Carey Guo) Monday: Cadence Report: "Hyperscale Computing Will Positively Impact Me within Five Years" Tuesday: Tensilica FloatingPoint DSP Family Wednesda...
- 4 Jul 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

I wish I could say there was something specific that stands out in this week’s compilation of CFD news. But it’s a fairly uniform compendium of CFD applications, software releases, company and tech introductions, computing insights, busi...
- 2 Jul 2021
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 8: Mixed-Signal Modeling Aspects of Verilog-AMS

Parula

This blog describes the behavioral modeling aspects of Verilog-AMS language that helps you to create and use modules for mixed-signal verification.
- 1 Jul 2021
Breakfast Bytes: Offtopic: John Muir Trail...and Weight

Paul McLellan

It is the last day before the July 4 break—Cadence is off on July 2 and 5, and I'm taking a day off on 6th too—so as is traditional before a break, I go off-topic. Before Memorial Day, I wrote about Kilimanjaro in my post "Pole Pole" to t...
- 1 Jul 2021
PCB設計／ICパッケージ設計: ASCENT: 回路図の監査機能で利用できる基本ルールについて

SPB Japan

このブログのパート1では、Allegro® System Capture の Design Integrity ソリューションをモデル無しで利用できるという点に焦点を当てて説明しました。今回は、パート2です。さて、回路設計でのエラーを確認するために200〜300ページにも及ぶデザインをスクロールしたり追跡したりすることは、ペンキが乾くのを見つめるのと同じ…ではないかもしれませんが、こんな共通点があります。”実際のところ、何時間も見つめていたい人なんているんでし...
- 1 Jul 2021
PCB設計／ICパッケージ設計: ASCENT: PCB部品の電気的ストレス、劣化、不具合を分析する

SPB Japan

部品の熱、ジュール熱、ヒートシンク…ボード上の何百ものデバイスについて、さまざまな動作条件でのストレスをチェックするというアイデアは、あなたがコーヒーブレイクをとれるための役に立ちそうですか？ ¼ワットの抵抗器が1/3ワットを消費していないか？ 50Vコンデンサが、100ボルトの一定のスパイクに悩まされていないか？ 100オーム抵抗の抵抗値は60度の温度においては115オームに変化するか？ 1ワットBJTの電力処理能力が、より高い温度においては0.75ワットまで低下...
- 1 Jul 2021
PCB、IC封装：设计与仿真分析: HDI 布线的挑战和技巧

TeamAllegro

什么是 HDI 布线? HDI（ High Density Interconnects，高密度互连）布线是指运用最新的设计策略和制造技术，在不影响电路功能的情况下实现更密集的设计。换句话说，HDI 涉及到使用多个布线层、尺寸更小的走线、过孔、焊盘和更薄的基板，从而在以前不可能实现的占位面积内安装复杂且通常是高速的电路。随着制造技术的发展，HDI 布线开始见于很多设计，如主板、图形控制器、智能手机和其他空间受限的设备。如果实施得当，HDI 布线不仅能大大减少设计空间，而且还减少了 PCB 上的 ...
- 30 Jun 2021
Analog/Custom Design: Spectre Tech Tips: Upgrading to SPECTRE 20.1

Stefan Wuensche

SPECTRE 19.1 ISR18, the last ISR of the SPECTRE 19.1 ISR release, was released on May 31st, 2021. This means that if you are still using the SPECTRE 19.1 release, you will not have access to any new features and enhancements made in Spectre. Read this blog to know more on how you can get the latest features and enhancements related to Spectre.
- 30 Jun 2021
Life at Cadence: Celebrating Pride Month at Cadence

Mary Kasik

Pride Month is a time for the LGBTQ+ community and allies to come together and celebrate the courage, resilience, and spirit of the LGBTQ+ community, recognizing the meaningful impact they’ve had on our history and culture. Pride Month is held ...
- 30 Jun 2021
System, PCB, & Package Design : BoardSurfers: Using Variables and Stacks in Allegro SKILL

Sanjiv Bhatia

In our previous blog post, we discussed how to count the number of pins and rename reference designators using the SKILL codes available in the Allegro SKILL Code Library. In this blog post, let’s focus on how to create a stack and define globa...
- 30 Jun 2021
System, PCB, & Package Design : IC Packagers: Understanding Stadium-Style Cavity Package Design

avijeet

Design complexity and space constraints are pushing designers to innovative novel solutions. Placing a die inside a cavity is the most common and effective technique and you have most probably used it if you are designing an application for the auto...
- 30 Jun 2021
Breakfast Bytes: CadenceLIVE Google Keynote: Please Sir, I Want Some Moore

Paul McLellan

The invited keynote for the first day of the recent CadenceLIVE Americas was by Partha Ranganathan, who is currently a VP and Engineering Fellow at Google where he is the area technical lead for hardware and data centers, designing systems at sc...
- 30 Jun 2021
PCB設計／ICパッケージ設計: Boardsurfers: Allegro DesignTrue DFM Rule Aggregatorで複数のDFMルールをマージ

SPB Japan

一つの設計会社が複数の基板製造メーカーと連携することは珍しくありませんが、製造メーカーは恐らく、それぞれが異なるDFMルールセットを必要とするはずです。そこで、設計会社の慣習として、すべての基板製造メーカーに適用できる、共通項となるルールセットを作成することがあります。このプロセスには時間がかかり、非効率的で、しかも、しばしば人為的ミスを誘発します。さらに、新しいテクノロジーや新たな製造業者を利用するたび、このプロセス全体を繰り返す必要があります。 Cadence®Allegro&reg...
- 29 Jun 2021
Breakfast Bytes: Tensilica FloatingPoint DSP Family

Paul McLellan

Recently, Cadence announced the availability of the Tensilica FloatingPoint DSP family. I expect you thought that Tensilica already had floating-point DSPs, and it is true that the existing Tensilica processors have an optional floating-point un...
- 29 Jun 2021
Life at Cadence: My Life at Cadence: Ludovic Perier

Lautanen

Cadence was recently recognized as Fortune and Great Place to Work® as one of the 2021 100 Best Companies to Work For®. This is Cadence’s seventh year in a row being named to this prestigious list, coming in at #65 this year. ...
- 28 Jun 2021
Breakfast Bytes: Cadence Report: "Hyperscale Computing Will Positively Impact Me within Five Years"

Paul McLellan

Do you know what hyperconnectivity is? It is already affecting you, whether you know it or not. Hyperscalers are the companies like AWS, Google, and Microsoft that build and run those enormous (aka hyperscale) data centers. If you are a designer and ...
- 28 Jun 2021
Analog/Custom Design: Virtuoso Meets Maxwell: Get Connected!

Brian LaBorde

One of the strengths of the Virtuoso RF solution is the ability to handle connectivity across multiple fabrics. We have recently extended some the IC tools you already know and have used. They now comprehend connectivity across a multi-fabric system. You can trace a physical net from the package into the ICs that it hosts, and use connectivity checking to ensure your system layout’s nets match your schematic.
- 28 Jun 2021
Breakfast Bytes: Sunday Brunch Video for 27th June 2021

Paul McLellan

https://youtu.be/nD_AYa2AbfU Made in my car (camera: my car's phone mount) Monday: Cadence global holiday Tuesday: Jim Hogan and Ed McCluskey Named Honorees of the Phil Kaufman Hall of Fame Wednesday: New Banknote with Alan Turing:...
- 27 Jun 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

It's Friday which means it's time to take a look back at what happened in the CFD world in the past week. This week's "must read" is an article from ACM Queue on programmer productivity. I recommend it for any who's a progra...
- 25 Jun 2021
Breakfast Bytes: June Update: PCIe 6.0, Ransomware, Mars, Turing Award...and CadenceLIVE

Paul McLellan

I have decided to put these "Update" posts that I do from time to time on a more regular basis. Going forward, they will appear on the last Friday of the month, unless that is a holiday or something, in which case I'll pull it forward a day or two. C...
- 25 Jun 2021
Analog/Custom Design: Virtuosity: Mystery Behind the .simrc File and Netlist Customization

Rashmi G

Read on to know the usefulness of the .simrc file and how and when it is picked by Virtuoso for netlist customization.
- 24 Jun 2021
Breakfast Bytes: Quantum Computing with Spectre's Ultra-Low Temperature Models

Paul McLellan

Equal1 has just announced a breakthrough in quantum computing with a fully integrated quantum processor operating at 3.7K using commercially available FD-SOI technology from GLOBALFOUNDRIES (GF) in Dresden, Germany. The chip was designed with Cadence...
- 24 Jun 2021
PCB、IC封装：设计与仿真分析: 动态电压和频率调节如何影响功耗

Sigrity

本文要点降低 CPU 或 GPU 功耗的技术有许多，这些技术聚焦软件/固件层面、系统层面和晶体管架构层面其中两种降低功耗的技术为：动态电压和频率调节，即调整电源电平、信号电平和时钟频率以响应功耗需求作为低功耗 VLSI （VLSI，超大规模集成电路）的一部分，动态电压和频率调节技术必须在硬件层面上实现当今的 CPU 能够处理的数据量比以往任何时候都要多，这要归功于摩尔定律的扩展和对更高级应用的需求不断增长。 2000 年Intel预测，如果按照线性推断，CPU 扩展将最终增加总功耗...
- 23 Jun 2021

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