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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

Breakfast Bytes

Congratulations Chris Rowen, for He's a Jolly Good (IEEE) Fellow

So the lede is that Chris Rowen has been elected an IEEE Fellow. In a sense it is…

• 4 min read
Chris Rowen , IEEE Fellow , RISC processors , Tensilica , configurable processors

Whiteboard Wednesdays

Whiteboard Wednesdays - Understanding the Computational Activity Behind Neural N…

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the inter-workings…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural network , pattern recognition

System, PCB, & Package Design 

What's Good About ADW’s Component Browser for Project Manager? The Secret's in the…

The 16.6-2015 Allegro Design Workbench (ADW) release contains a significant enhancement…

• 1 min read
Allegro 16.6 , Allegro Design Workbench , Library flow , Library and design data management , SPB , component browser , design data management , PCB design , Grzenia , Librarians , library , ADW , Allegro

Breakfast Bytes

EDAC "Crossing the Chasm" with John Lee

EDAC's Emerging Companies Committee has been organizing evening seminars a couple…

• 6 min read
John Lee , EDAC , EDA standards , Jim Hogan , Ansys

Breakfast Bytes

IEDM: the International Electron Devices Meeting

IEDM is a meeting held annually since 1955. Historically, it has alternated between…

• 4 min read
International Electron Devices Meeting , IEDM , semiconductors , Breakfast Bytes

Breakfast Bytes

EUV Might Really Happen

I have been a skeptic about whether EUV was going to work. Just in case you have…

• 4 min read
lithography , 5nm test chip , defect , pellicle , 7nm , EUV , Breakfast Bytes

Academic Network

First Cadence Academic Network Workshop in Israel

On October 27, the Cadence Academic Network organized the 1st Cadence Academic Workshop…

• 1 min read
university , Cadence Academic Network , academic workshop , Bar Ilan University

Whiteboard Wednesdays

Whiteboard Wednesdays - Implementation of Multi-Link, Multi-Protocol PHY

In this week's Whiteboard Wednesdays video, William Chen deep dives into the implementation…

• less than a min read
Whiteboard Wednesdays , multiprotocol PHY , PHY IP

Breakfast Bytes

Use the Integrated Flow with US

A couple of years ago, it was clear that the Cadence implementation flow required…

• 4 min read
Genus , full-flow , Joules , Voltus , Innovus , Quantus QRC , Quantus , integrated flow , Breakfast Bytes

Academic Network

Cadence Academic Network Presents at Khalifa Semiconductor Research Center

On Nov. 18 Dr. Patrick Haspel presented at Khalifa Semiconductor Research Center…

• 1 min read
Cadence Academic Network , UAE , Khalifa

Academic Network

Using Constraints Generation When Designing Power-Constrained SoCs

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling…

• 3 min read
constraints generation , Professor Farid Najm , power constrained SoCs , power grid , Power Integrity , voltage drop , power scheduling

Breakfast Bytes

Rob Aitken of ARM Research on System Design

I wrote yesterday of how there is a transition going on as system companies discover…

• 2 min read
SDE , system design , Rob Aitken , system design enablement , ARM , Breakfast Bytes

Academic Network

Why Agile Software Methodologies Can Improve the Chip Design Process

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer…

• 3 min read
Berkeley engineering , AMS , agile software development , open source , mixed signal , UC Berkeley

Academic Network

Cadence Tech Days at ITMO and MIET

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies…

• 1 min read
MIET , Cadence Academic Network , Russia , ITMO

Breakfast Bytes

Applications Down to Transistors: System Design Enablement

Last year Dan Nenni and I wrote a book on the semiconductor industry through the…

• 5 min read
SDE , fabless , moore's law , system design enablement , Breakfast Bytes , foundry

Academic Network

10th Cadence Design Contest 2015 Successfully Organized in India

Cadence India organized the 10th edition of the Cadence University Program’s flagship…

• 1 min read
EDA , Cadence Design Contest , India , university program

Academic Network

Xtensa Design Contest 2015 in India

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University…

• less than a min read
Cadence Academic Network , Cadence India , Xtensa Design Contest , university program

Academic Network

Cadence Innovus Implementation System is Available to Academia

To support academia using the latest industry-standard tools, Innovus™ Implementation…

• 1 min read
Routing , academia , Innovus , implementation , Placement

Breakfast Bytes

Front-end Design Summit

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses…

• 4 min read
Genus , Encounter Test , manufacturing test , Joules , front end design summit , Test , front end design , Synthesis , power , Breakfast Bytes
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