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Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI
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Blog - Post List

Latest blogs

Breakfast Bytes

Sunday Brunch Video for 13th October 2019

https://youtu.be/8BM28qwHyUk Made at Arm TechCon (camera Randy Smith) Monday: What…

• less than a min read
Breakfast Bytes

PCB、IC封装：设计与仿真分析

5G系统的PCB材料和设计要求

即将到来的5G时代迫使设计师对于移动设备和物联网设备的PCB设计进行着重新思考。这些5G系统将使大多数消费者的设备运行速率达到新高度。当我们对电路板提出通信要求时…

• less than a min read
5G , RF , Chinese blog , 系统设计 , PCB Designer , PCB设计 , 中文

Breakfast Bytes

Sensor Fusion and ADAS in TSMC Automotive Processes

At the recent TSMC OIP Symposium, Cadence's Tom Wong presented Sensor Fusion and…

• 4 min read
OIP , Automotive , sensor fusion , TSMC , lidar , radar , Tensilica , vision , camera , ADAS

Breakfast Bytes

The Economist on RISC-V and Indian Semiconductors

Our industry is difficult to understand. Most of us resort to imperfect analogies…

• 8 min read
risc-v , The Economist , CDNLive India , India

Analog/Custom Design

Virtuosity: Device-Level Routing for Advanced Nodes—Tree Route Flow

This is the last blog in the Virtuoso Device-level routing blog series and completes…

• 4 min read
tree routing , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

The First Woman to Receive the Kaufman Award

Mary Jane Irwin just got back from a cruise around the Greek islands with her husband…

• 5 min read
Kaufman Award

定制IC芯片设计

Virtuosity：Automated Device Placement and Routing — 基于 WSP 的树型设备布线

此博客概述了 Virtuoso Automated Device Placement and Routing解决方案的最后一步。在本博客中，我将介绍Automated…

• less than a min read
automatic routing , Chinese blog , tree routing , Automated Device Placement , ICADVM18.1 , EXL , Automated Device-Level Placement , VPR , Automatic Placement , Virtuoso Placer , Auto Device P&R , Auto P&R , Tree Route , Virtuoso , Virtuosity , Virtuoso Placement , Placement , Custom IC Design , space based router , Virtuoso Layout Suite EXL , Virtuoso Layout Suite

定制IC芯片设计

Virtuosity：自动设备放置和布线*基础层填充插入

欢迎回到我在Virtuoso Automated Device Placement and Routing 系列的下一篇文章。在advanced nodes上，在运行放置器后…

• less than a min read
automatic routing , device fill , Chinese blog , device fills , Cadence blogs , Automated Device Placement , ICADVM18.1 , Virtuoso Advanced Release , Automated Device-Level Placement , Automatic Placement , Advanced Node , Virtuoso Placer , Auto Device P&R , Layout EXL , Auto P&R , Virtuoso , Virtuosity , Virtuoso Placement , fills , base layer fill , Custom IC Design , Virtuoso Layout Suite , Custom IC

Whiteboard Wednesdays

Whiteboard Wednesdays - The Need for Electro-Thermal Co-simulation

In this week's Whiteboard Wednesdays video, Tom Hackett explains the need for electrical…

• less than a min read
CFD , Celsius Thermal Solver , Whiteboard Wednesdays , 3D IC , FEM , Computational Fluid Dynamics , Thermal Analysis , finite element analysis , FEA

Academic Network

4th Tensilica Day(s!) in Hannover: Doubling the Days, Doubling the Fun

The popularity of the Tensilica day events in previous years (last year's presentations…

• 3 min read
Leibniz Universität Hannover , Cadence Academic Network , academic workshop , academia , EDA , Tensilica , ADAS , neural networks

System, PCB, & Package Design 

IC Packagers: Undoing Your Custom SKILL Commands

Today, we’ll talk about something simple but still important. For all of you who…

• 3 min read
APD , SiP Layout , SKILL

Academic Network

First Ever China Integrated Microsystem Simulation and Modeling Master Thesis Co…

Cadence Academic Network was the exclusive sponsor of the first ever China Integrated…

• 1 min read
university , Cadence Academic Network , academia , Academic Network , university program

Breakfast Bytes

It's Ada Lovelace Day Today

The second Tuesday in October is Ada Lovelace Day (ALD). This is not just a day to…

• 6 min read
analytical engine , ada , ada lovelace , Babbage

Analog/Custom Design

Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is it even possible!? (Part…

You heard it right! Virtuoso now supports Package and Board level designs; therefore…

• 4 min read
SiP , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Package Design in Virtuoso , Electromagnetic analysis , Virtuoso , RF design , Custom IC Design , Allegro

Breakfast Bytes

What Is Quantum Supremacy?

There are rumors that Google has achieved quantum supremacy. According to Scott Aaronson…

• 4 min read
quantum computing , IBM , quantum supremacy , google

Breakfast Bytes

Sunday Brunch Video for 6th October 2019

https://youtu.be/zEmNTM72GYE Made at Sawyer Camp Trail (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Academic Network

Student Story: Min-Chun's Contribution to Cell-Aware Test

Let me introduce myself. My name is Min-Chun Hu, a master student majoring in electrical…

• 2 min read
Cadence interns , Interns , Cadence Academic Network , pegasus , modus , imec , Spectre , Quantus

PCB、IC封装：设计与仿真分析

关于PCB设计倒角需要了解的一切

将任意一个角落切掉，便能得到一个倒角。从儿童防护桌到泰姬陵的标志性外墙，人类通过倒角来解决与角相关的功能和美学问题由来已久。 使两个表面以90°以外的角度，尤其是45…

• less than a min read
PCB , Chinese blog , PCB设计 , 中文 , Allegro PCB Editor , Allegro , 倒角

Breakfast Bytes

EDA in the Cloud: Astera Labs, AWS, Arm, and Cadence Report

Earlier this week I wrote a post covering the AWS presentation from HOT CHIPS about…

• 6 min read
cloud , aws , cadence cloud , Liberate , Amazon
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