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Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

Corporate
• 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
• 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Corporate News

Accelerating System Design with Real-Time Simulation, Powered by AI Physics

Rising demand for AI infrastructure is driving faster innovation and smarter use…

Corporate
• 4 min read
CFD , featured , NVIDIA , accelerated compute , millennium
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Life at Cadence

LPDDR5X: Why Mobile Memory Matters More than Ever

Since its ratification in the mid-2000s, low-power DDR (LPDDR) has been fundamental…

• 5 min read
featured , lpddr5x , Denali

Breakfast Bytes

Cadence's DDR Portfolio...and LPDDR5X-8533

At the recent CadenceLIVE Europe, Marc Greenberg presented Cadence's portfolio of…

• 5 min read
ddr5 , Memory , featured , DRAM , lpddr5 , DDR

Digital Design

Voltus Voice: Dulce Domum and Happy Holidays!

A recap of the power integrity posts in the Voltus Voice blog series through 2022…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , Power-Efficient Design , hierarchical power integrity analysis , Thermal Integrity , Power Analysis , vector profiling , vectorless

System, PCB, & Package Design 

The Year That Was: Cadence PCB & Package Design Blogs and Videos in 2022

Another year has gone by, and we continue to evolve with the new normal, inching…

• 1 min read
BoardSurfers , 22.1 , (P)SpiceItUp , PSPICE , IC Packagers , Allegro Package Designer , 17.4-2019 , Training Insights , Allegro System Capture , Allegro PCB Editor , ASCENT , Allegro

Digital Design

Voltus Voice – How to Step Up Your Game with Target Power Vectorless Dynamic EMIR…

Check out this blog to learn how you can perform accurate modelling of localized…

• 5 min read
Voltus IC Power Integrity Solution , Power Target Vectorless EMIR , Power Integrity , Power-Efficient Design , Digital Implementation , Power Analysis , signoff , vectorless , dynamic power

Breakfast Bytes

December Update: Chenming Hu, Leap Seconds, Right to Repair, and More

Cadence will be shut down on the last Friday in December, so despite this being only…

• 7 min read
transistors , Apple , update , power , right to repair

Computational Fluid Dynamics

On-Demand Webinar: LMG Marin Cuts Time and Costs in Ship Design Using Fine Marin…

LMG Marin is a naval architecture design and engineering office working on commercial…

• 1 min read
CFD , Marine Engineering , marine design , webinars , marine , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software

Computational Fluid Dynamics

Women in CFD with Fanny Besem-Cordova

For the December post of the Women in CFD series, we have Fanny Besem-Cordova, principal…

• 6 min read
CFD , Pointwise , fluid dynamics , WomenAtCadence , Fidelity CFD , women in engineering , simulation software , NUMECA , Women in CFD

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: パッケージ・レイアウトからパッケージ回路図を自動生成できるのですか？

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
IC Packaging , Footprint , VRF , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso MultiTech , Package Design in Virtuoso , Virtuoso , RF design , japanese blog

Analog/Custom Design

Knowledge Booster Training Bytes – Place and Route Using Virtuoso Placer

Do you know you can do placement of the devices by using Virtuoso Placer, which helps…

• 6 min read
Advanced Node , Virtuoso Placer , analog/mixed-signal , Custom IC Design , Virtuoso Layout Suite EXL , Row-Based Placement

Breakfast Bytes

RISC-V Summit Day 2: Krste, Android

My first post about the recent RISC-V Summit appeared last week: RISC-V Summit 2022…

• 4 min read
risc-v , featured , risc-v summit , risc-v foundation

Spotlight Taiwan

Cadence一舉囊括亞洲金選獎(EE Awards)五項大獎!

由電子工程領域專業媒體《EE Times》及《EDN》出版集團ASPENCORE台灣/亞洲團隊主辦之第二屆亞洲金選獎(EE Awards Asia)在12月8日盛大圓滿落幕…

• less than a min read
Taiwan , system analysis , taiwanese blog , intelligent system design , integrity3DIC

Verification

Demonstrating PCIe 6.0 Equalization Procedure

The Link equalization procedure enables components to adjust the Transmitter and…

• 4 min read

Computational Fluid Dynamics

Last Week at Fidelity CFD

Let's take one last look during 2022 of what's happening here at Fidelity CFD. From…

• 3 min read
CFD , Marine Engineering , FINE Marine , turbomachinery , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , cadencelive , Mesh Generation

Life at Cadence

Accelerating the Move to Society 5.0

Our world has gone through many transformations, and technology is accelerating these…

• 3 min read
Industry 4.0 , society 5.0 , intelligent system design

Breakfast Bytes

IEDM Keynote: Ann Kelleher on Future Technology

IEDM 2022 celebrated 75 Years of the Transistor. I wrote about it myself in my post…

• 4 min read
Intel , featured , IEDM , iedm 2022

Computational Fluid Dynamics

Adhering to User Preferences with Entity Selection

It is often a cumbersome task to select the entities that ought to be modified individually…

• 4 min read
CFD , user preferences , Meshing Monday , engineering , simulation software , entity selection , Mesh Generation , Cadence CFD , Fidelity Pointwise

Verification

SD Host Controller for SD Card Verification

SD Host Controller was introduced to transfer data to SD Card from system memory…

• 2 min read
Verification IP , host , Memory , VIP , SD

RF /マイクロ波設計

μWaveRiders:成功するAWR Design Environmentでの設計 - レイアウトと部品ライブラリ

When starting a new design, it's important to take the time to consider design recommendations…

• 1 min read
RF Simulation , Circuit simulation , AWR Design Environment , awr , Component library , Layout , microwave office , japanese blog , Visual System Simulator(VSS)
CDNS - Fix Layout Hompage