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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design

In this blog we would like to let you know – amongst other things - how to implement…

• 3 min read
training , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC

カスタムIC／ミックスシグナル

Virtuoso Video Diary: Virtuoso Visualization and Analysis XLのTabular Graph

読者の皆様、こんにちは。 今回は、Virtuoso Visualization and Analysis XLのエキサイティングな機能であるTabular Graphについてご紹介したいと思います…

• less than a min read
Analog Design Environment , ViVa-XL , custom/analog , ADE Explorer , Analog Simulation , ADE , Virtuoso , ViVA , Virtuosity , japanese blog , Custom IC Design , ADE Assembler

Breakfast Bytes

Cadence/Samsung Automotive Reference Flow

Today, Cadence and Samsung announced the availability of an Automotive Reference…

• 6 min read
Automotive , Genus , functional safety , Safety , Samsung , samsung foundry , Innovus , fusa , reliability

Breakfast Bytes

Benedict Evans on Tech in 2021

Benedict Evans used to work in Silicon Valley for Andreesen-Horowitz (a16z) but he…

• 6 min read
benedict evans , Internet

System, PCB, & Package Design 

BoardSurfers: Installation Know-How: Using Third-Party Tools with Cadence OrCAD and…

The add-on model is applicable everywhere! You can choose a basic version of the…

• 5 min read
Installation Know-How , 17.4 , cadence , install , BoardSurfers , Allegro OrCAD Installer , 17.4-2019 , Download Manager , OrCAD , Allegro

Breakfast Bytes

Gall's Law and Big Ball of Mud

Gall's Law says: A complex system that works is invariably found to have evolved…

• 4 min read
design patterns , software development

Analog/Custom Design

Virtuoso Video Diary: Incremental Simulations with Enhanced Reference Histories and…

Gone are the days of exporting results from multiple interactive runs and combining…

• 4 min read
Analog Design Environment , ICADVM18.1 , Analog Design Environment , Virtuosity , Virtuoso Video Diary , Custom IC , IC6.1.8 , Assembler , ADE Assembler

Spotlight Taiwan

RF/微波設計 隨選豐富影片信手拈來!

Cadence 團隊為客戶精選從去年至今年RF/微波設計一系列精采演講，內容涵蓋Cadence如何整合RF/微波設計的產品組合，提供市場上最全面的RF設計解決方案…

• less than a min read
5G , awr , EMX , taiwanese blog

Breakfast Bytes

Dynamic Duo 2: The Sequel

There's a story, probably apocryphal, about a screenwriter pitching a movie in Hollywood…

• 6 min read
dynamic duo , prototyping , protium x2 , palladium z2 , Emulation , FPGA prototyping , software development , firmware development

Computational Fluid Dynamics

This Week in CFD

It’s a good Friday for the latest roundup of CFD flotsam and jetsam from the ocean…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

System, PCB, & Package Design 

ASCENT: Ready, Steady, Design ... Even With Existing Libraries

After a quick overview of Allegro® System Capture , let’s start at the very beginning…

• 3 min read
System Capture , 17.4 , cadence , logical design , Allegro Unified Libraries , 17.4-2019 , Front-end PCB design , logic-capture , PCB design , Allegro System Capture , ASCENT , Schematic , Allegro

Breakfast Bytes

Offtopic: Podcasts

Tomorrow is another Cadence global holiday. None of us will be working and Breakfast…

• 8 min read
offtopic , podcast

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3D Solverで受動素子と能動素子を持つRFブロックをシミュレートするには？

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
AXIEM , VLS EXL , EM Solver , Virtuoso Meets Maxwell , Electromagnetic analysis , black boxing , Virtuoso , EMX , ICADVM20.1 , japanese blog , Clarity 3D Solver , Virtuoso Layout Suite EXL

カスタムIC／ミックスシグナル

Start Your Engines: SimVision Mixed-Signal Debug Optionを使ってル・マンで優勝する

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , Start Your Engines , simvision , analog/mixed-signal , Virtuoso , AMSD Flex Mode , japanese blog , mixed-signal design , debugging , mixed-signal verification

Computational Fluid Dynamics

Resolving Boundary Layers with Unstructured Quad and Hex Meshing: On-Demand Webi…

All things being equal, CFD practitioners prefer to use hexahedral mesh cells in…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Breakfast Bytes

The First Commercial Computer Shipped 70 Years Ago Today

Today is the 70th anniversary of a very significant event in all our lives, even…

• 5 min read
first computer , univac

System, PCB, & Package Design 

(P)SpiceItUp: Generating ISO 7637-2 Standard Pulse 2a in PSpice A/D

Many times, you would have required to create a standard pulse waveform that can…

• 2 min read
17.4 , OrCAD Capture , PSpiceA/D , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD

Digital Design

Library Characterization Tidbits: Define Measurements to Suit Your Characterization…

Do you have a requirement to specify measurements that are not default while performing…

• 3 min read
memory characterization , define_measure , Liberate MX , Library Characterization Tidbit , Liberate Characterization Portfolio

定制IC芯片设计

Virtuoso Meets Maxwell：为什么没有提到引线键合IC？

当今的许多模拟，RF和混合信号设计都要求在同一模组内部集成多个不同工艺的IC，以实现所需的性能目标。设计师使用异构器件集成方法能够获得单片IC (SoC) 设计上不容易达到的结果…

• 1 min read
Chinese blog , ICADVM18.1 , Co-Design , Virtuoso System Design Environment , Virtuoso RF Solution , Wirebond , Electromagnetic analysis , Virtuoso , Custom IC Design , Allegro
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