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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

カスタムIC／ミックスシグナル

Start Your Engines: ミックスシグナルシミュレーションでTclコマンドをより効果的に使う

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• 1 min read
save statement , AMS , AMS Designer , AMSD , Start Your Engines , Spectre AMS Designer , Mixed-Signal , probe , xcelium , japanese blog

Analog/Custom Design

Virtuoso Studio: In-Design Verification with iPegasus

By Olivier Arnaud, Product Engineering Group Director, Cadence. Today's complex SoC…

• 5 min read
Symmetric Fill , Virtuoso Studio , DRC , metal fill , Custom IC

Analog/Custom Design

Virtuoso Studio: iPegasus for Signoff DRC and Fill

The semiconductor world is evolving. The number of design rules is increasing, and…

• 6 min read
Pegasus Verification System , Virtuoso Studio , Pegasus Interactive , in-design verification , iPegasus , Signoff DRC , Custom IC Design , IC23.1

Artificial Intelligence (AI)

Learn How Labforge Is Bringing AI into Vision Systems

Labforge is a Waterloo, Ontario-based company that designs, builds, and manufactures…

• less than a min read
artificial intelligence , Vision P6 , Tensilica , AI

Corporate News

DAC Celebrates Its 60th Anniversary

The Design Automation Conference (DAC) recently celebrated its 60th anniversary in…

• 6 min read
Allegro X AI , DAC , artificial intelligence , cadence.ai , Generative AI , verisium , Cadence Cerebrus , GenAI , AI

Computational Fluid Dynamics

AESIN TECH TALK: Accurate Electro-Thermal Simulation for Thermal Management of Electric…

In this AESIN TECH TALK, Matt Evans, Principal Product Engineer at Cadence, will…

• 1 min read
CFD , Automotive , TechTalk , AESIN , Celsius EC Solver , electric drivetrain , engineering , simulation software

Computational Fluid Dynamics

Discover What’s New in Fine Marine CFD

The newest version of Fine Marine offers critical enhancements that improve solver…

• 2 min read
CFD , Marine Engineering , FINE Marine , naval architecture , marine , fine/marine , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , CFD Applications , simulation software

Data Center

Sustainable Design of Data Centers Using Cadence Reality DC

In the CadenceLIVE Silicon Valley presentation on From Chips to Chillers: Electronics…

• 5 min read
data center , Celsius EC Solver , digital twin , Electronics cooling , Computational Fluid Dynamics , simulation software

System, PCB, & Package Design 

BoardSurfers: Creating GUIs Using Allegro SKILL

The Allegro SKILL coding language offers capabilities to create user-friendly graphical…

• 12 min read
BoardSurfers , 22.1 , PCB Editor , Allegro PCB Editor , SKILL

Artificial Intelligence (AI)

Renesas Collaborates on Large Language Model Generative AI Chip Design

Renesas and Cadence have been collaborating for several years, combining their expertise…

• 2 min read
featured , LLM , cadence.ai , cerebrus , Renesas

Academic Network

Academic and Entrepreneur Tracks at CadenceLIVE Europe 2023

I am very happy to announce that registration for the in-person CadenceLIVE Europe…

• 3 min read
Student Design Teams , Master Thesis Award , Proof-of-Concept , Academic Track , CadenceLive Europe

Analog/Custom Design

How Much Do You Know About Virtuoso Studio?

How much do you know about Virtuoso Studio? Here are the answers to the True or False…

• 5 min read
featured , Virtuoso , analog design , Custom IC

Verification

Verification of Integrity and Data Encryption (IDE) for CXL Devices

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre FMC Analysisのご紹介

プロセスが微細化するにつれて、デバイスのミスマッチが回路性能に与える影響は大きくなり、現在では、このミスマッチが性能指標に与える影響を解析するために、さらに多くのモンテカルロ…

• 1 min read
Spectre Circuit Simulator , Monte Carlo analysis , Spectre Fast Monte Carlo , japanese blog , Virtuoso ADE Assembler , ADE Assembler

Learning and Support

From Learners to Innovators: Inside Cadence’s Certified Training Partner Program

The news is replete with stories of a global shortage of engineers, which is only…

• 2 min read
coverage , debug , Signoff Timing and Power Analysis , Cadence training , Cadence certified , Training Partners , Languages and Methodologies , simulation , Digital Physical Design , Synthesis and Static Timing Analysis

定制IC芯片设计

Virtuosity: Virtuoso Design Intent支持多语言注释

ICADVM20.1 ISR20 开始，用户可以使用普通话、日语、印度语等非拉丁字符的语言来编写 Design Intent 中的注释。

• less than a min read

Computational Fluid Dynamics

Automatically Generate the Best Mesh Each Time with Adaptive Grid Refinement

The goal of simulation preprocessing is to create a mesh that is suitable for the…

• 5 min read
Computational Fluid Dynamics , simulation software , Mesh Generation , Cadence CFD , Adaptive Grid Refinement , Fidelity Pointwise

Digital Design

Training Webinar: A Revolutionary Approach to Optimizing Chip Design

Please join me, Cadence Training and Application Engineer Krishna Atreya, for this…

FormerMember • 1 min read

Analog/Custom Design

Start Your Engines: Use Tcl to Save Signals More Efficiently in AMS Simulations

For large SoC designs, the simulation performance might get impacted by the number…

• 3 min read
save statement , AMS , AMS Designer , AMSD , Start Your Engines , Spectre AMS Designer , Mixed-Signal , probe , xcelium
CDNS - Fix Layout Hompage