Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Wondering What to Do During the Winter Staycation? How about Learning Something New…

We just recently released a training course that we are excited to tell you about…

• 1 min read
conformal , Genus , Tempus , modus , Voltus , Digital Implementation , Innovus

System, PCB, & Package Design 

BoardSurfers: Training Insights: Running RAVEL Rules from Command Line

In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI…

• 3 min read
17.4 , Cadence Online Support , 17.4-2019 , PCB design , Allegro PCB Editor , Allegro

Digital Design

SSV 20.2 Base Release Now Available

The SSV 20.2 production release is now available for download at Cadence Downloads…

• 2 min read
Signoff ECO , Tempus PI , Timing analysis , Tempus Timing Signoff Solution

System, PCB, & Package Design 

IC Packagers: Comparing Design Versions to Find Physical Changes

ECOs. Without them, the lives of designers would be so much easier! Imagine a world…

• 6 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy

Fast growing markets like 5G, automotive, and IoT are driving the development of…

• 6 min read
Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Electromagnetic analysis , EMX , Quantus Extraction Solution , RF design , ICADVM20.1 , Custom IC Design , VMM

Breakfast Bytes

Instruction Decoders: RISC vs CISC

In my post The Start of the Arm Era I said that it feels like something significant…

• 9 min read
Intel , ARM

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power— Virtuoso Power Managerのセットアップ

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
Virtuoso Schematic Editor , virtuoso power manager , Conformal Low Power , VPM , Supply States , setup , Virtuoso , Virtuosity , ICADVM20.1 , japanese blog , mixed-signal design , Custom IC Design , power domains

Digital Design

Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the…

This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis…

• 2 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , electrical-thermal , Digital Implementation , FinFET , self-heating effects , IR drop , Full-Chip

Life at Cadence

My Life at Cadence: Dimitra Papazoglou

Cadence embraces multiculturality and diversity as an important part of our One Team…

• 1 min read
cadence , WomeninTech , WomenAtCadence , LifeAtCadence

Breakfast Bytes

Avoiding PCB Respins with Better Computational Software

When I first came to the US, I started at VLSI Technology supporting a project called…

• 5 min read
Celsius Thermal Solver , celsius , Clarity 3D Transient Solver , Clarity 3D Solver , clarity

Breakfast Bytes

Sunday Brunch Video for 13th December 2020

https://youtu.be/ZcYIbkrHSv4 Made by my Christmas tree (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Life at Cadence

Highlighting Our Girl Geeks at Cadence!

Last month, Cadence partnered with Girl Geek X for the first time, hosting a virtual…

• 1 min read

System, PCB, & Package Design 

BoardSurfers: Managing Materials Using A Single Material File for PCB, Package, and…

Legacy material editors supported different file formats leading to inconsistencies…

• 5 min read
17.4 , Allegro Package Designer , 17.4-2019 , Allegro PCB Editor , SI analysis and modeling

Breakfast Bytes

HBI, a New Standard to Connect Your Chiplets

It is not very well-known how involved Cadence is in establishing standards. Recently…

• 4 min read
hbi , highbandwidth interconnect , 3DIC , more than Moore , d2d , openhbi

カスタムIC／ミックスシグナル

Virtuosity: Virtuoso ADE Verifierでの検証 - 信頼性の方法!

数年前、私たちは改善および刷新されたVirtuoso ADE Verifierをリリースしました。その様々な利点に親しんで頂いているに違いないと確信しています。ビデオ…

• 1 min read
verifier , Analog Design Environment , Cadence blogs , ICADVM18.1 , custom/analog , Analog Simulation , verification plan , analog , ADE , Mixed-Signal , reliability options , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso , Virtuosity , implementations , mixed signal , Verifier Run Plan , japanese blog , reliability analysis , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , reliability , Assembler , Verifier new feature , ADE Assembler , verification

Breakfast Bytes

The 2020 RISC-V Summit

The second week of December was RISC-V week, the three-day RISC-V summit (or four…

• 5 min read
risc-v

RF /マイクロ波設計

μWaveRiders:AWR電磁界シミュレータは設計の成功のために複雑なRF/マイクロ波の構造を解析

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence…

• less than a min read
RF , AWR simulation , AWR Analyst , AWR Design Environment , awr , EM simulation , AWR EM Simulators , Electromagnetic(EM) , Electromagnetic analysis , AWR AXIEM , Analyst 3D FEM EM Simulator , AXIEM 3D Planar Simulator , japanese blog , simulation

Breakfast Bytes

Photonics: How Do You Attach Fiber to the Chip?

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution…

• 6 min read
silicon photonics , photonics

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: システム解析と実装を可能にするためのライブラリ構築

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Technology Independent Layout Pcell , Unified Library , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Electromagnetic analysis , librarian , SiP Layout Option , ICADVM20.1 , Cadence SiP Layout , TILP , japanese blog , Custom IC Design , VMM
CDNS - Fix Layout Hompage