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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

カスタムIC／ミックスシグナル

Virtuosity: Voltus-Fiの最小抵抗パスに沿って移動する

ここに、私たちがおそらく考えたこともないような思考のラインがあります: 私たちは川のようなものです。私たちは抵抗の少ない道を選んで人生を歩んでいます。私たちは皆そうします…

• less than a min read
Voltus-Fi , electromigration , EMIR Analysis , power grid , Voltus-Fi-XL , Virtuoso , voltage drop , ICADVM20.1 , japanese blog , LRP , Custom IC Design , Custom IC , IC6.1.8

System, PCB, & Package Design 

IC Packagers: A Final Set of Reasons to Move to 17.4 HotFix 013

I could doubtless extend this series all year long, covering the important updates…

• 5 min read
IC Packaging and SiP , 17.4 QIR2 , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Early Firmware Development at Kioxia America

At CadenceLIVE, Kioxia's Ravi Tangirala presented System-Level Emulation and Prototyping…

• 4 min read
Protium , Palladium , Toshiba , firmware , kioxia

カスタムIC／ミックスシグナル

Start Your Engines: Real NumberからElectricalへの変換のためのミックスシグナル・モデリングのベストプラクティス

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• 1 min read
R2E conversion , real number modeling , mixed signal design , AMS Designer , Start Your Engines , real to electrical , japanese blog

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power—Conformal Low Powerを使ったデザインの検証

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
Virtuoso Schematic Editor , virtuoso power manager , clp , Conformal Low Power , VPM , Supply States , 1801 , setup , Virtuoso , Virtuosity , ICADVM20.1 , UPF , japanese blog , IEEE , mixed-signal design , Liberty , Custom IC Design , power domains

Breakfast Bytes

The Best of CES 2021

There is a whole portfolio of official "best of CES" awards, 14 of them this year…

• 5 min read
Consumer Electronics Show , CES , AMD

Breakfast Bytes

Sunday Brunch Video for 24th January 2021

https://youtu.be/WeiohMmcwzc Made at "some waterfalls" Monday: MLK Day Tuesday…

• less than a min read
sunday brunch

Breakfast Bytes

CES 2021: AMD, NVIDIA, and Mercedes

This is my second post about this year's CES. The first was Consumer Electronics…

• 7 min read
Consumer Electronics Show , CES , AMD , NVIDIA , Samsung , mercedes-benz

Life at Cadence

My Life at Cadence: Emmanuelle Amouriaux

We have recently interviewed some of our EMEA team members to hear about their unique…

• less than a min read
my life at cadence , cadence emea

Breakfast Bytes

Modus DFT Has Been ISO 26262 Certified by TÜV-SÜD

At the end of last year, Cadence's Modus DFT Software Solution was ISO 26262 certified…

• 5 min read
DFT , modus , tüv-süd , Test , ISO 26262 , certification

カスタムIC／ミックスシグナル

Virtuosity: Voltus-Fi-XLでのWhat-Ifメカニズムの解読

‘What if?’ は、仮想的なシナリオに有益な考えを誘導することを目的とした、小さいながらも強力な質問です。実際、それは私たちの想像力を飛躍させ、潜在的な出来事の理解を高め…

• less than a min read
EMIR Analysis , debug , Voltus-Fi-XL , what-if analysis , Virtuoso , Virtuosity , ICADVM20.1 , japanese blog , Custom IC Design , IC6.1.8 , EMIR

System, PCB, & Package Design 

BoardSurfers: Training Insights: Three Ways to Start OrbitIO System Planner

OrbitIO System Planner is a multi-fabric interconnect planning and optimization solution…

• 3 min read
17.4 , Cadence Online Support , OrbitIO System Planner , 17.4-2019

The India Circuit

Gowri Shankar: A Story of Overcoming Obstacles to Achieve Success

Shy and reticent Gowri Shankar is possibly the personification of the old saying…

• 1 min read
CadenceCares , CadenceScholarshipProgram , cadence

Breakfast Bytes

Cadence to Acquire Computational Fluid Dynamics Company NUMECA

This morning, Cadence announced that it was acquiring NUMECA International to expand…

• 2 min read
CFD , featured post , Computational Fluid Dynamics , NUMECA , Omnis

System, PCB, & Package Design 

IC Packagers: More Reasons to Move to 17.4 HotFix 013

As promised, we’re back with some more of the big improvements that are part of the…

• 4 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Consumer Electronics Show 2021: GM, Intel

Normally, at this time of year I would be in Las Vegas, as I have been in January…

• 5 min read
Intel , Consumer Electronics Show , CES , general motors

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power—パワーインテントのインポートとエクスポート

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
Virtuoso Schematic Editor , virtuoso power manager , Conformal Low Power , VPM , Supply States , 1801 , setup , Virtuoso , Virtuosity , ICADVM20.1 , UPF , japanese blog , IEEE , mixed-signal design , Liberty , Custom IC Design , power domains

Breakfast Bytes

Sunday Brunch Video for 17th January 2021

https://youtu.be/mKoW8ji9_g8 Made in my kitchen (camera Ziyue Zhang) Monday: Young…

• less than a min read
sunday brunch

Breakfast Bytes

Offtopic: How to Make Spatchcock Chicken Under a Brick

It's Martin Luther King Day on Monday. Cadence is off. Breakfast Bytes will not appear…

• 3 min read
offtopic
CDNS - Fix Layout Hompage