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New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
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Blog - Post List

Latest blogs

カスタムIC／ミックスシグナル

Virtuosity: Conserve Power— インデザイン・チェックの実行

Conserve Powerは、ローパワー検証の世界を垣間見ることができるブログ・シリーズです。デザインのパワーインテントを指定し管理することができるVirtuoso…

• less than a min read
In-Design Checks , Low Power , virtuoso power manager , Schematic XL , in-design , VPM , Schematic Editor , ICADVM20.1 , UPF , Power Manager , mixed signal , japanese blog , Liberty , Custom IC Design

RF /マイクロ波設計

2021年1月 オンラインワークショップ - 増幅器設計の機能を体験

2021年1月 オンラインワークショップ ケイデンスオンラインセミナーでは、高周波設計のソリューションを定期的に紹介しています。今回はソフトウェアを利用しながら…

• less than a min read
RF , awr , japanese blog

Breakfast Bytes

Off Topic: "Beam Me Up, Scotty" and Other Things Nobody Said

T his is my end-of-year off-topic holiday post, traditional before a break or a holiday…

• 6 min read
offtopic

カスタムIC／ミックスシグナル

Virtuoso Video Diary: デジタル信号のユーザビリティ改善

私達は、ユーザビリティに対してのアイデアが製品を使いやすく、アクセスをさらに容易にし、視覚的に魅力的なものにする世界に住んでいます。製品の使いやすさを向上させるために…

• less than a min read
Mnemonic Map , Cadence blogs , ICADVM18.1 , simvision , analog , Virtuoso Visualization and Analysis XL , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuoso Video Diary , ICADVM20.1 , Configure Mnemonics , usability , japanese blog , Custom IC , IC6.1.8

Digital Design

Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring…

Hi everyone, Searching for yet another method to improve the QoR of your design…

• 3 min read
blended training , Genus , training bytes , Digital Implementation , online training , Cadence support

Breakfast Bytes

Breakfast Nibbles: How Did My 2020 Predictions Turn Out?

Every year I make a few predictions about trends for the coming year. I will be doing…

• 5 min read
5G , Automotive , predictions , cloud , more than Moore , cadence cloud , autonomous vehicles

定制IC芯片设计

Virtuoso Meets Maxwell: Clarity 与有限元方法结合

本文将介绍Clarity 的一些功能，当你需要使用基于FEM的电磁解算器用于 Virtuoso RF 解决方案时，Clarity 将会是您 的最佳选择！

• 1 min read
EM Analysis , Chinese blog , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Clarity 3D , Electromagnetic analysis , ICADVM20.1 , Finite Element Method , Virtuoso Layout Suite , clarity

Digital Design

Library Characterization Tidbits: Bidding Adieu to 2020

This year all our “regular” routines were shaken up by COVID-19, which brought along…

• 2 min read
library characterization , Library Characterization Tidbit , Digital Implementation , Liberate Characterization Portfolio

カスタムIC／ミックスシグナル

Virtuosity: Voltus-Fi-XL FAQ — よくある質問とその回答

読者のみなさん、こんにちは！ Voltus-Fiに関する蒸留された知識をお探しなら、正しいページにお立ち寄りいただきました！ 何年にもわたって好奇心を持ち続け、さまざまなプラットフォームでのVoltus…

• less than a min read
ICADVM18.1 , Voltus-Fi-XL , PGV , Electromagnetic analysis , japanese blog , IR drop , Custom IC Design , IC6.1.8 , EMIR

Analog/Custom Design

Virtuosity: Moving Along the Least-Resistive Path in Voltus-Fi

Do you want to know how discovering the path of least resistance for the devices…

• 4 min read
Voltus-Fi , electromigration , EMIR Analysis , power grid , Voltus-Fi-XL , Virtuoso , voltage drop , ICADVM20.1 , LRP , Custom IC Design , Custom IC , IC6.1.8

Life at Cadence

Chiplets and Heterogeneous Packaging Are Changing System Design and Analysis

In the domain of electronic product design, solely relying on process shrink as the…

• 10 min read
chiplets , 3D-IC , heterogeneous integration

Breakfast Bytes

RISC-V: The Next Ten Years

The annual RISC-V Summit (virtual, of course) was in early December. You can read…

• 10 min read
risc-v

Analog/Custom Design

Spectre Tech Tips: Increasing Performance and Capacity Using Spectre X Distributed…

The Spectre X distributed simulation is an extension to the multithreaded simulation…

• 5 min read
multithreaded simulation , ppn , Multi-Core , XDP , spectre x , Spectre X distributed simulation , multithreaded

RF Engineering

μWaveRiders: Cadence AWR EM Simulators Solve Complex RF/Microwave Structures for…

RF designers increasingly rely on electromagnetic (EM) simulations to characterize…

• 3 min read
RF , AWR simulation , AWR Analyst , AWR Design Environment , awr , EM simulation , AWR EM Simulators , Electromagnetic analysis , Electromagnetic (EM) , AWR AXIEM , Analyst 3D FEM EM Simulator , AXIEM 3D Planar Simulator , simulation

Digital Design

Wondering What to Do During the Winter Staycation? How about Learning Something New…

We just recently released a training course that we are excited to tell you about…

• 1 min read
conformal , Genus , Tempus , modus , Voltus , Digital Implementation , Innovus

System, PCB, & Package Design 

BoardSurfers: Training Insights: Running RAVEL Rules from Command Line

In one of the previous posts, we learnt about How to Run a RAVEL Rule from the GUI…

• 3 min read
17.4 , Cadence Online Support , 17.4-2019 , PCB design , Allegro PCB Editor , Allegro

Digital Design

SSV 20.2 Base Release Now Available

The SSV 20.2 production release is now available for download at Cadence Downloads…

• 2 min read
Signoff ECO , Tempus PI , Timing analysis , Tempus Timing Signoff Solution

System, PCB, & Package Design 

IC Packagers: Comparing Design Versions to Find Physical Changes

ECOs. Without them, the lives of designers would be so much easier! Imagine a world…

• 6 min read
IC Packaging and SiP Design , 17.4 , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy

Fast growing markets like 5G, automotive, and IoT are driving the development of…

• 6 min read
Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Electromagnetic analysis , EMX , Quantus Extraction Solution , RF design , ICADVM20.1 , Custom IC Design , VMM
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