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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

CadenceLIVE: Do You Know What CMP Is?

I was talking to someone at Cadence recently and I was surprised that he didn't know…

• 4 min read
CMP

System, PCB, & Package Design 

Shift Left: Moving Multiphysics into the Mainstream

As electronic systems have grown incrementally more complex, with more features packed…

• 1 min read
in-design analysis , Electromagnetic analysis , Signal Integrity , Thermal Analysis , microwave design

Breakfast Bytes

Andreas Kuehlmann and Tortuga Logic...I Mean Cycuity

I was in San Francisco for the RSA security conference. On Monday, it has tutorials…

• 2 min read
tortuga logic , cycuity , common weakness enumeration

RF /マイクロ波設計

μWaveRiders:新しいPythonライブラリは、Cadence AWR Design Environmentで高レベルのAPIを提供します

新しいPythonライブラリは、Pythonのコーディング規則により厳密に準拠したコマンド構造を使用して、PythonとAWRソフトウェア間のインターフェイスを容易にするために作成されました…

• less than a min read
RF Simulation , Circuit simulation , AWR Design Environment , Graphing measurements , awr , Graphs , Tips/Tricks , Circuit Design , microwave office , japanese blog , measurements , Visual System Simulator(VSS)

Breakfast Bytes

June Update: CHIPS, Minis, and DI Water

My monthly update normally occurs on the last Friday of the month. But for June,…

• 4 min read
Intel , mini , di water , motorcycles , chips act

Verification

Xcelium PowerPlayBack App and Dynamic Power Analysis

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay…

• 5 min read
Dynamic Power Analysis , xcelium , power

Breakfast Bytes

Sunday Brunch Video for 17th July 2022

https://youtu.be/ogP4BoGLEW4 Made with Lumen5 Monday: Cadence Acquires Future Facilities…

• less than a min read
sunday brunch

System, PCB, & Package Design 

Ascent: Training Insights: Managing Design Variations in Allegro System Capture

Assembling the board is one of the last yet crucial steps in the PCB development…

• 4 min read
System Capture , 17.4 , design variant , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Allegro

Breakfast Bytes

Cadence and MathWorks Announce Flow from MATLAB to RTL

Today in Yokohama at CadenceLIVE Japan, Cadence announced a new MATLAB/Stratus flow…

• 4 min read
Mathworks , Stratus , HLS , Matlab

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Cadence Celsius Thermal Solver: A Complete Thermal…

This blog introduces Cadence Celsius Thermal Solver, the industry’s first complete…

• 5 min read
Sigrity and Systems Analysis , CFD , Celsius Thermal Solver , thermal management , PDN , Power Dissipation , Thermal Basics , 3DIC , IC package design , Computational Fluid Dynamics , PCB design , Air Cooling , FEA

カスタムIC／ミックスシグナル

Spectre Tech Tips: 精度101

Spectreを含むアナログ回路シミュレータは、求める測定値に応じてシミュレータのパラメータをパッケージとして切り替え、最適な精度と性能のバランスを得るための精度モードが用意されています…

• less than a min read
Analog Simulation , accuracy , analog , vabstol , Spectre , Simulators , iabstol , japanese blog , reltol , spectre x , Spectre X Simulator

Breakfast Bytes

DAC 2022: Day 3

On to day 3 and the final day that I will be posting about. My posts on the first…

• 12 min read
bespoke silicon , DAC , 49dac , Design Automation Conference

Computational Fluid Dynamics

New Tricks from the Old Towing Tank

Towing a ship model into a humongous basin of water allows naval architects to identify…

• 6 min read
maneuvering , marine design , Pointwise , Cadence Fidelity , CFD Applications , engineering , simulation software , NUMECA , seakeeping , towing tank

Breakfast Bytes

DAC 2022: Day 2

I covered Day 1 (and Day 0) of the Design Automation Conference in my post yesterday…

• 15 min read
59dac , DAC , Design Automation Conference

Verification

Jasper C2RTL App for Datapath Verification

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every…

• 5 min read
Datapath Verification , c2rtl , Jasper C2RTL , Equivalence Checking

Computational Fluid Dynamics

GPPS 2nd Turbomachinery CFD Workshop Evaluates RANS Solvers

The GPPS 2nd Turbomachinery CFD workshop, co-organized by Cadence, will take place…

• 1 min read
turbomachinery , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , rank-n , nlh

Breakfast Bytes

DAC 2022: Day 1

It's the Design Automation Conference and it is taking place in person in San Francisco…

• 7 min read
59dac , DAC , dac 2022 , troublemaker panel , john cooley , Design Automation Conference

Verification

Cadence in Collaboration with Arm Ensures the Software Just Works

The increase in compute and data-intensive applications and the need for lower power…

• 6 min read
SBSA , Emulation , Pre Silicon compliance Testing , Arm SystemReady

Digital Design

Voltus Voice: Overcoming Design Challenges Using Voltus Documentation—The Definitive…

This post facilitates easy access to the Voltus Help and Documentation through the…

• 3 min read
digital badge , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , training bytes , Digital Implementation , Cadence Education Services
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