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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 7: The Virtuoso ADE…

This blog shows how to efficiently use the Virtuoso ADE Assembler and Virtuoso ADE…

• 4 min read
blended , ADE Explorer , Explorer , training , Cadence training , digital badges , training bytes , Virtuoso , Analog IC Design videos , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training , Custom IC , Assembler , ADE Assembler

Computational Fluid Dynamics

This Week in CFD

It's Friday which means it's time for that weekly roundup of news from the CFD world…

• less than a min read
CFD , Pointwise , fine/marine , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing

Computational Fluid Dynamics

Hello, CFD Meshing World!

For the third time*, I find myself writing the obligatory, "Hello, World!" first…

• 2 min read
CFD , Pointwise , Computational Fluid Dynamics , NUMECA , Mesh Generation , Meshing

Digital Design

What’s Inside the GUI-Based Timing Report in Genus? Want to Explore?

Timing closure is one of the most crucial steps of a digital design. Therefore, to…

• 1 min read
report , Genus , gui , timing debug , Timing Optimization , debug report , Synthesis

Breakfast Bytes

Sunday Brunch Video for 2nd May 2021

https://youtu.be/1HEd6JCriCQ Made in Groveland CA (camera Carey Guo) Monday: Package…

• less than a min read
sunday brunch

System, PCB, & Package Design 

IC Packagers: Analyze, Simulate, and Resolve Signal Integrity Issues Using In-Design…

In today's ever-shrinking IC Package design cycles, it is almost imperative that…

• 3 min read
IDA , IC Packaging and SiP , IC Packagers , Allegro Package Designer , 17.4-2019 , PCB design

Breakfast Bytes

Offtopic: Miniatur Wunderland

Tomorrow and Monday are Cadence Global Holidays. Of course, May 1 is a holiday anyway…

• 4 min read
offtopic

Verification

What Disruptive Changes to Expect from PCI Express Gen 6.0

PCIe (Peripheral Component Interconnect Express) has long been the backbone of complex…

• 3 min read
SoC verification , Functional Verification , Modeling , verification

Breakfast Bytes

Arm V9A

Yesterday, I wrote about rapid adoption kits (RAKs) for the latest Arm server-class…

• 4 min read
isa , arm v9 , ARM

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: ICパッケージングプロセスのためのダイとBGAパッケージ間の接続の作成

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
IC , package , Footprint , Virtuoso Meets Maxwell , Virtuoso RF Solution , Package Design in Virtuoso , Allegro Package Designer Plus , BGA , die , OrbitIO , SiP Layout Option , ICADVM20.1 , japanese blog , Ball , Custom IC , bump

Breakfast Bytes

Rapid Adoption of the Arm Server-Class Processors

Arm has been moving from its foundational base in mobile into the data center, with…

• 3 min read
featured post , neoverse-v1 , neoverse , verification suite , digital full flow , neoverse-n2 , ARM

System, PCB, & Package Design 

ASCENT: Finding the Right Parts with Unified Search

Some people say that finding the right components for a design is the most time-consuming…

• 4 min read
System Capture , 17.4 , cadence , Dashboard , Search , logical design , LIVE BOM , logic capture , 17.4-2019 , PCB design , Allegro System Capture , Unified Search , New part request , ASCENT , BOM , Schematic , Allegro

Analog/Custom Design

Spectre Tech Tips: Introducing Electrothermal Simulation

Understanding the thermal performance of integrated circuits has been essential to…

• 3 min read
Electrothermal simulation , Spectre , Custom IC Design , Legato Reliability

Computational Fluid Dynamics

Thermal Analysis of a Hardware Blade System

Here's a video titled Thermal Analysis of a Hardware Blade System. The "blade system…

• less than a min read
CFD , celsius , protium x1

Breakfast Bytes

Package Assembly Design Kits

At the recent IMAPS conference, Cadence's John Park presented on Package Assembly…

• 3 min read
system in package , imaps , packaging , chiplet , adk , PDK

Breakfast Bytes

Sunday Brunch Video for 25th April 2021

https://youtu.be/ZuxS3yM7RCw Made at Communication HIll, San Jose (camera/drone…

• less than a min read
sunday brunch

Verification

What Is New in the Latest AMBA 5 ACE, AXI and AHB Protocol Specification Updates…

The industry-standard ARM AMBA® 5 protocol specifications continue to evolve, further…

• 1 min read
amba5 , Functional Verification , ACE5 , AXI5 , AMBA VIP , AMBA Verification IP , AHB5

Computational Fluid Dynamics

This Week in CFD

This week’s compilation of CFD news begins with a must-read article on how to choose…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Digital Design

Pegasus: Get Your Wings: Strong Immunity Makes Pegasus Fault Tolerant

We all know the importance of good immunity and how a good immune system makes you…

• 1 min read
Pegasus Verification System , Fault Tolerance , pegasus , signoff , silicon signoff
CDNS - Fix Layout Hompage