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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

CDNLive: Testing Times in Munich

Test is the red headed step child of EDA. FinFETs, self-aligned quadruple patterning…

• 9 min read
modus test , CDNLive , Scan test , modus , imec , Test

Academic Network

Status of Verification Education in Academia

Since I’ve started working for Cadence Academic Network three years ago, when talking…

• 3 min read
survey , Cadence Academic Network , Functional Verification , young professionals , Incisive simulator

Breakfast Bytes

Agile Development of Custom Hardware

It was back in 2016 that I first heard about RISC-V, and the Raven implementation…

• 5 min read
bag , chisel , agile software development , waterfall , raven , agile hardware development , UC Berkeley , Agile

Breakfast Bytes

Compromising a Fortune 500 Company...Without Hacking a Thing

Rachel Tobac and Joe Gray opened their talk at RSA by highlighting how important…

• 6 min read
security , rsa conference , rsa , social engineering

System, PCB, & Package Design 

Power-Aware SI DDR4 Simulation: You Have a Choice!

Simultaneous switching noise (SSN) caused by simultaneous switching outputs (SSO…

• 4 min read
Speed2000 , DDR4 , FDTD , power-aware , SystemSI , SSN

Breakfast Bytes

CDNLive EMEA, Driving to the Future

This week it has been the 13th European CDNLive, held in Unertschleißheim in the…

• 7 min read
Automotive , legato , CDNLive , CDNLive EMEA , AI

System, PCB, & Package Design 

Make Reliable Designs That Won’t Fail In The Real World!

Heard about the ongoing recalls in the Automotive and Cellphone industry? Let's address…

• less than a min read
RF , OrCAD Capture , PSPICE , PCB design , simulation

Breakfast Bytes

Digital Marketing in EDA...with No Hands on the Wheel

Years (decades) ago, Robert Townsend, the CEO of Avis, faced a problem. Hertz was…

• 5 min read
google , YouTube , digital marketing , Twitter , adwords , onespin , esd alliance

Whiteboard Wednesdays

Whiteboard Wednesday - Introducing the DFI 5.0 Interface Standard

In this week’s Whiteboard Wednesday, John MacLaren, chairman of the DDR PHY Interface…

• less than a min read
DDR Controller , Whiteboard Wednesdays , DDR PHY

Breakfast Bytes

Legato: Smooth Reliability for Automobiles

In his keynote at ICCAD in 2014, Bosch's VP engineering Peter van Staa said that…

• 4 min read
legato , CDNLive , CDNLive EMEA , reliability

Breakfast Bytes

What's For Breakfast? Video Preview May 14th to 18th 2018

https://youtu.be/T4Pu_l6upso Coming from Englischergarten Munich (camera Andy…

• less than a min read
bag , CDNLive , efpga , chisel , CDNLive EMEA , TSMC , TSMC Technology Symposium , FPGA

Breakfast Bytes

TSMC's Fab Plans, and More

The TSMC Technology Symposium took place recently. I grouped all the process and…

• 5 min read
gigafab , TSMC , TSMC Technology Symposium

Breakfast Bytes

TSMC Technology Symposium 2018

This week it was the TSMC Technology Symposium in Silicon Valley. Dave Keller, president…

• 9 min read
n5 , TSMC , TSMC Technology Symposium , n7+ , n7 , 5nm , 7nm

Verification

Leading the Charge: Cadence Announces New Verification IP for UFS 3.0, CoaxPress…

Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence…

• 1 min read
hyperRAM , Functional Verification , coaxpress , UFS , press release

Breakfast Bytes

What's For Breakfast? Video Preview May 7th to 11th 2018

https://youtu.be/OJRKUHltc1c Coming from Teske's Germania (camera Sean) Monday…

• less than a min read
CDNLive EMEA , TSMC , TSMC Technology Symposium , digital marketing , social engineering , esd alliance

Breakfast Bytes

The San Jose Tech Museum

Last summer, I did a series of posts about technology museums. If you missed them…

• 6 min read
security , san jose , the tech , body worlds

Breakfast Bytes

DDR5 IP Test Chip Operates with Micron Prototype DRAM at 4400 MT/s

The DDR5 standard has not been finalized by JEDEC, and they are very strict about…

• 4 min read
ddr5 , DDR4 , TSMC , DRAM , DDR , 7nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Tensilica DSPs, Sensors, and Neural Networks

In this week’s Whiteboard Wednesdays video, the last in a three-part series, Robert…

• less than a min read
Automotive , Whiteboard Wednesdays , sensor fusion , lidar , radar , camera , ADAS

Verification

How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary…

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary…

• 2 min read
DDR Controller , Verification IP , ddr5 , DDR4 , TSMC Tech Symposium , TSMC , DDR , DDR PHY
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