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Breakfast Bytes

RSA 2020: From Sulu to Penn & Teller

I attended the RSA Conference in San Francisco recently. I guess that is going to…

Paul McLellan 19 Mar 2020 • 6 min read

security , rsa conference , rsa

System, PCB, & Package Design

IC Packagers: Design Element Label Management

A few weeks ago, we talked about template text labels for design-specific information…

Tyler 18 Mar 2020 • 4 min read

Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design

BoardSurfers: Creating Footprints Using Templates in Library Creator

With ECAD-MCAD Library Creator, you can easily create footprints for your parts using…

Sanjiv Bhatia 18 Mar 2020 • 3 min read

Library Creator , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

Breakfast Bytes

How Intel Manufactures Chips

I happened to be looking for something on YouTube recently when I came across this…

Paul McLellan 18 Mar 2020 • 3 min read

Intel , fab

定制IC芯片设计

Virtuosity：回顾定制IC芯片设计博客的黄金时代

如果您错过了2019 发布的Virtuosity, Virtuoso Meets Maxwell 和Virtuoso Video Diary等博客专栏，或者您想了解已发布ISR中的增强功能…

Dishika Majumdar 17 Mar 2020 • less than a min read

Chinese blog , ICADVM18.1 , Automated Device-Level Placement and Routing , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Virtuosity , Custom IC Design , Virtuoso Layout Suite , Custom IC

Analog/Custom Design

Virtuosity: Device Arrays in the Automated Device Placement and Routing Flow

Since the release of the Automated Device Placement and Routing solution last year…

Sravasti 17 Mar 2020 • 3 min read

Modgen On Canvas , ICADVM18.1 , MODGEN , Automated Device-Level Placement and Routing , APR Modgen , Advanced Node , auto device array , APR , Auto P&R , advanced nodes , ada , Custom IC Design , Custom IC

System, PCB, & Package Design

New 3D Analysis Engine Offers Faster, More Accurate Simulations at Lower Cost

A multi-CPU architecture running on both cloud and on-premise computers can better…

Sigrity 17 Mar 2020 • 6 min read

PCB , IC , 3D full wave extraction , 3D analysis , IC package design , Sigrity , High Speed design , clarity

Breakfast Bytes

Digital Full Flow for 5/7nm

One constant in the semiconductor and EDA industries is, of course, Moore's Law.…

Paul McLellan 17 Mar 2020 • 4 min read

Genus , P&R , Tempus , Voltus , Innovus , digital full flow , Synthesis , full flow

Analog/Custom Design

Virtuoso Meets Maxwell: Bumps, Bumps.... Where Are My Bumps?

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection…

Brian LaBorde 16 Mar 2020 • 3 min read

ICADVM18.1 , Edit-in-Concert , Co-Design , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , stacked solution , Custom IC Design , bumps

Breakfast Bytes

Another Year of CadenceLIVE—with Updated Schedule

It's not strictly true that it is another year of CadenceLIVE since we called the…

Paul McLellan 16 Mar 2020 • 3 min read

CDNLive , cadencelive

Verification

RAK Attack: Better Driver Tracing, Faster Palladium Build Time, UVM Register Map…

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online…

XTeam 14 Mar 2020 • 2 min read

Rapid Adoption Kit , IXCOM , RAK , Indago , JasperGold

Breakfast Bytes

Another Year, Another Book of Breakfast Bytes

There is a new edition of A Year of Breakfasts. How do you get a copy? You can get…

Paul McLellan 13 Mar 2020 • 3 min read

a year of breakfasts , book

The India Circuit

Is Every Day Really Women's Day? Yes And No.

This week had a plethora of posts and articles on International Women's Day (IWD…

Madhavi Rao 12 Mar 2020 • 2 min read

Women Of Cadence , International Women's Day , EachForEqual , Women in Technology

Breakfast Bytes

Breakfast Nibbles: Predictions for 2020...Plus How Did I Do in 2019?

Last year in my post Breakfast Nibbles: Predictions for 2019 , I made various predictions…

Paul McLellan 12 Mar 2020 • 3 min read

5G , Automotive , predictions , deep learning , cloud , EUV , nibbles

System, PCB, & Package Design

BoardSurfers: Training Insights: Creating Custom Reports using ‘Extract’

You must deal with many reports in your daily life – for your health, financial accounts…

Shreyansh 11 Mar 2020 • 2 min read

Allegro PCB Editor

Breakfast Bytes

Exponential Growth

In the semiconductor industry, we've been dealing with the exponential growth associated…

Paul McLellan 11 Mar 2020 • 5 min read

exponential , rule of 70 , moore's law

System, PCB, & Package Design

IC Packagers: The Different Types of Mirrors

I’m not talking about carnival funhouse mirrors, but rather the different options…

Tyler 10 Mar 2020 • 7 min read

Allegro Package Designer

Breakfast Bytes

The Future's So Bright You've Gotta Wear Shades

The Cadence website looks different, doesn't it? We are obviously in the middle of…

Paul McLellan 10 Mar 2020 • 2 min read

computational software , website , intelligent system design , branding

Analog/Custom Design

Virtuoso Meets Maxwell: Common Goal for One Flow, Acquisitions Strengthen RF Flo…

Seven months ago, I pointed out the ongoing need for change, or revolution, in high…

michaelthompson 9 Mar 2020 • 3 min read

integrand , ICADVM18.1 , Virtuoso New Design Platform , awr , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Advanced Node , Virtuoso RF , Electromagnetic analysis , EMX , RF design , microwave office , Custom IC Design , Virtuoso Layout Suite , acquisitions

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