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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

MLPerf: Benchmarking Machine Learning

Most presentations at the recent HOT CHIPS conference are about actual chips, mostly…

• 6 min read

Analog/Custom Design

Virtuosity: Layout Reuse Flow in Modgen

Modgen now supports the Layout Reuse Flow. Read on to see how you can use this feature…

• 4 min read
Modgen On Canvas , ICADVM18.1 , MODGEN , Layout Suite , Layout , Virtuoso , Virtuosity , Layout design , Custom IC Design , modgens , Virtuoso Layout Suite , Custom IC

System, PCB, & Package Design 

DATA Pulse: Track Your Components—Efficient Library and Design Data Management

Ever noticed how some objects always mysteriously disappear? It's like they have…

• 1 min read
lifecycle , RAK , Allegro

Breakfast Bytes

Sunday Brunch Video for 15th September 2019

https://youtu.be/bcAO52jxk10 Made at SFO (camera Carey Guo) Monday: HOT CHIPS: In…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

Ken的博客系列之六 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：高效的互连提取 使用IBIS-AMI模型进行仿真 此时，SerDes元器件供应商应该已经提供了所需的IBIS-AMI模型…

• less than a min read
PCB , SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , equalization , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性

Breakfast Bytes

Intelligent System Design

Yesterday in my post Intelligent Systems , I wrote about how the imperative for differentiated…

• 5 min read
system analysis , pervasive intelligence , design excellence , intelligent system design , system innovation

Breakfast Bytes

Intelligent Systems

Cadence's goal is to empower engineers at semiconductor and systems companies to…

• 4 min read
intelligent system design

Digital Design

Safety and Aging in IoT Devices: What We Know Today

How do we achieve highly accurate aging data models for critical circuits in automotive…

• 1 min read
iot devices , DAC 2019 , aging , GlobalFoundries

定制IC芯片设计

Virtuosity: Spring-Cleaned Virtuoso Doc Closet

如需了解IC6.1.8 和ICADVM18.1相关的最新文档，请继续阅读.

• less than a min read
legato , Chinese blog , Virtuoso Schematic Editor , ICADVM18.1 , Routing , ADE L , Virtuoso RF , Layout EXL , layout XL , Layout L , Cadence Help , Virtuoso Doc , Virtuoso Design Environment , New in EDA , Virtuoso Layout Suite EXL , IC6.1.8

Breakfast Bytes

EDPS Preview 2019

EDPS, the Electronic Design Process Symposium, is coming up next Monday. It will…

• 3 min read
deep learning , 3DIC , EDPS , more than Moore , AI

Life at Cadence

How to Land a Job at Cadence: Recruiters Share Their Best Tips for Standing Out and…

As we send off the last of our 2019 Summer Interns ( read more about their experience…

• 4 min read
intern , Student , internship

System, PCB, & Package Design 

IC Packagers: How Far Away are You?

Layout design is all about clearances. Daily challenges come from maintaining consistent…

• 3 min read
SiP Layout

System, PCB, & Package Design 

BoardSurfers: PCB Electronics - Electrical Constraints

Whether it's NASA's space missions or a school camping trip; building a cutting-edge…

• 3 min read
Constraint Manager , Allegro Package Designer , Allegro PCB Editor , SiP Layout

Analog/Custom Design

Virtuoso IC6.1.8 ISR6 and ICADVM18.1 ISR6 Now Available

The IC6.1.8 ISR6 and ICADVM18.1 ISR6 production releases are now available for download…

• 2 min read
Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , Automated Device-Level Placement and Routing , Automatic Placement , Interactive and Assisted Routing , IC Release Announcement blog , Virtuoso RF , Layout EXL , ADE , Mixed-Signal , Layout , Virtuoso , advanced nodes , New in EDA , Virtuoso EM Solver , Custom IC Design , Virtuoso Layout Suite , Custom IC , ADE Verifier , IC6.1.8 , ADE Assembler

Breakfast Bytes

CDNLive India 2019: NXP and More

Last week I covered Day 1 of CDNLive India . Today it is the turn of verification…

• 6 min read
NXP , CDNLive India , CDNLive

Analog/Custom Design

Virtuoso Meets Maxwell: Add Some MAGic to Your ElectroMAGnetic Analysis

If you’ve ever seen a great magician at work, you know that their talent lies in…

• 4 min read
ICADVM18.1 , Virtuoso New Design Platform , video , Virtuoso Meets Maxwell , Virtuoso RF , Electromagnetic analysis , EM Analyis , RF design , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

HOT CHIPS: In-DRAM Compute

Something that has been discussed for years is the fact that we could add processors…

• 4 min read
pim , hot chips , processor in memory

Verification

Dimensions to Verifying a USB4 Design

Verification of a USB4 router design is not just about USB4 but also about the inclusion…

• 2 min read
Verification IP , Router , DisplayPort , USB , usb4 , PCIe , USB3 , tunneling

Breakfast Bytes

Sunday Brunch Video for 8th September 2019

https://youtu.be/AvimlRMDZng Made at Cadence parking lot (camera Steve Brown) Monday…

• less than a min read
sunday brunch
CDNS - Fix Layout Hompage