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Breakfast Bytes

Will Crypto Change the World?

Do you remember when you had to pay for ringtones? In 2005, analysts were predicting…

Paul McLellan 8 Feb 2019 • 12 min read

crypto , Internet , mobile , blockchain

Analog/Custom Design

Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET De…

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda…

Hiro Ishikawa 7 Feb 2019 • 4 min read

Analog Design Environment , Virtuoso New Design Platform , Physical placement and layout , Advanced Node , Virtuoso , Custom IC Design

System, PCB, & Package Design

Simulation for a Song: Downloading Models from the Web and Associating with Parts…

While on a long drive, I like to sing along; say Eye of the Tiger or Johny B Goode…

mrigashira 7 Feb 2019 • 3 min read

capture , Models , PSPICE , OrCAD , simulation

Analog/Custom Design

Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further…

Cutting-edge innovation … Top-down planning … Reliable and formalized verification…

Rashmi G 7 Feb 2019 • 3 min read

verifier , PVT , ICADVM18.1 , custom/analog , Formalized Verification , Analog Simulation , ADE , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , space , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler , verification

Breakfast Bytes

60 Years of DARPA—61 Actually

On 4th August 1957, the Soviet Union launched the first artificial satellite, Sputnik…

Paul McLellan 7 Feb 2019 • 5 min read

Aerospace , magestic , arpa , space , eri , darpa , chips

Analog/Custom Design

Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download…

Virtuoso Release Team 6 Feb 2019 • 2 min read

Analog Design Environment , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , ADE , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Virtuoso: The Next Overture , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Breakfast Bytes

DesignCon 2019

It doesn't seem to matter what a show is ostensibly about at the moment. Every show…

Paul McLellan 6 Feb 2019 • 4 min read

uber , DesignCon , AMI , IBIS , 112g , photonics

定制IC芯片设计

Virtuosity: 如何使用ADE Explorer 及ADE Assembler 打开旧版本的ADE 状态和视图文件

您是否发现，当您查看 Virtuoso ® ADE L 状态（State）文件，或者 Virtuoso ® ADE XL 视图 (View) 文件时，默认打开程序仍然是旧版本的…

NamrataM 5 Feb 2019 • 1 min read

Chinese blog , Analog Design Environment , Virtuoso ICADVM18.1 , ICADVM18.1 , ADE Explorer , ADE Migration , maestro , ADE , Virtuoso IC6.1.8 , Virtuoso ADE Explorer , Virtuoso ADE Assembler , IC6.1.8 , ADE Assembler

Breakfast Bytes

Emerging Memories Poised to Explode

A couple of weeks ago was the Persistent Memory Summit. (For more details, see my…

Paul McLellan 5 Feb 2019 • 5 min read

fram , ReRAM , flash , xpoint , 3D NAND , NAND flash , emerging memories , DRAM , nor flash , MRAM , PCRAM

Breakfast Bytes

DesignCon: Cadence Teaches AMI and IBIS

At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced…

Paul McLellan 4 Feb 2019 • 9 min read

DesignCon , AMI , IBIS , SerDes

PCB、IC封装：设计与仿真分析

2019七大行业动向预测

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “ Breakfast Nibbles: Predictions…

SDA China 3 Feb 2019 • less than a min read

5G , Chinese blog , 内存 , 无人车 , 3nm , 电动车 , DRAM , 中文 , 汽车 , 云 , 5nm , 神经网络 , AI , EUV

Breakfast Bytes

Sunday Brunch Video for 3rd February 2019

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM:…

Paul McLellan 3 Feb 2019 • less than a min read

5G , DFT , Memory , CES , modus , mobile , persistent memory , IEDM

Breakfast Bytes

Programming Persistent Memory

I talked earlier this week about the recent persistent memory summit (see my post…

Paul McLellan 1 Feb 2019 • 5 min read

programming model , persistent memory

Analog/Custom Design

Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

An important requirement for project sign-off is to ensure that all the design simulations…

Yagya Mishra 31 Jan 2019 • 2 min read

verifier , PVT , coverage , Analog Coverage , Analog Simulation , Virtuoso Analog Design Environment , space , Custom IC Design , Assembler , verification