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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

カスタムIC／ミックスシグナル

Virtuoso Studio IC23.1がリリースされました

Virtuoso Studio IC23.1の製品リリースが Cadence Downloads からダウンロードできるようになりました。サポートされているプラットフォームやその他のリリースの互換性情報については…

• 2 min read
Cadence blogs , Virtuoso Studio , IC Release Blog Announcement , IC Release Blog , japanese blog , Custom IC Design , Cadence Community , IC23.1

Verification

Understanding PCIe 6.0 Shared Flow Control

As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms…

• 3 min read
SystemVerilog , Verification IP , PCIe , pcie gen6 , PCIe 6.0 , System Design and Verification , verification

Analog/Custom Design

Virtuoso ICADVM20.1 ISR33 and IC6.1.8 ISR33 Now Available

The ICADVM20.1 ISR33 and IC6.1.8 ISR33 production releases are now available for…

• 2 min read
Cadence blogs , Virtuoso , ICADVM20.1 , IC Release Blog , Custom IC Design , IC6.1.8 , Cadence Community

Digital Design

3D-IC: The Future of Integrated Electronics Is the Future of Electronics Itself

According to Gordon E. Moore, “The future of integrated electronics is the future…

• 2 min read
3D-IC , 2.5DiC , IC layout , 3DIC RAKs , training bytes , C4 Bump , Digital Implementation , TSVs , Innovus , 3D-IC Technology , 3DIC vs 2.5DIC , interposer , heterogenous integration , RAKs , 3D-IC High_Level_Presentation , IC design , 3DIC References

Computational Fluid Dynamics

Boost Your CFD Workflow Productivity with the Fidelity Python API – Part III

Welcome back to the third and final part of this blog series! In this blog post,…

• 3 min read
workflow productivity , CFD , automation , Python API , Fidelity CFD , engineering , simulation software , Mesh Generation

System, PCB, & Package Design 

BoardSurfers: Training Insights: Reducing Time to Market with Allegro DesignTrue…

Allegro DesignTrue DFM rules help you perform fabrication, assembly, and test checks…

• 5 min read
Cadence Online Support , 22.1 , DesignTrue DFM , Constraint Manager , PCB design , Training Insights , Allegro PCB Editor , DFM , Allegro

Cloud

Flying High Above the Cloud with Cadence

The semiconductor industry has long been ambivalent about embracing cloud technology…

• 4 min read
Managed Cloud , cloud , cadencelive

Corporate News

Importance of Diversity in Generative AI: Ensuring Ethical and Inclusive Technol…

Generative AI is an exciting field that has the potential to revolutionize many industries…

• 4 min read
Insights on Culture , inclusion , Culture , ai-driven , diversity , AI

Corporate News

EDA’s New Dimension of Design: As Moore’s Law Slows, the Industry Moves to 3D-ICs…

I’ve been thinking lately about the legacy of Gordon Moore, the late Intel co-founder…

• 4 min read
3D-IC

Analog/Custom Design

Virtuoso Meets Maxwell: Custom Passive Device Authoring - Part 1 (Automatic Marker…

You probably heard about the release of Cadence EMX Designer. This blazing fast layout…

• 7 min read
EM simulation , Virtuoso Meets Maxwell , Virtuoso RF Solution , Electromagnetic Solver , Virtuoso Multi-Technology Solution , Custom IC Design , IC23.1

Analog/Custom Design

Start Your Engines: Debugging Mixed-Signal Partitioning Issues Using the Elabora…

Mixed-signal partitioning issues are a common occurrence in mixed-signal functional…

• 6 min read
real coercion , real number modeling , AMS , mixed signal design , debug , Elaborator , AMS Designer , detailed discipline resolution , Mixed-Signal , analog/mixed-signal , AMS simulation , wreal , AMS Verification , mixed-signal verification

Verification

CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performanc…

Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The…

• 1 min read
Mixed-Signal , xcelium simulator , xcelium

Corporate News

Tessolve Is Reinventing Touch-Sense Controls

Imagine you’re trying to get your way back home in snowy weather, and you’re trying…

• 2 min read
cloud , designed with cadence , cadence cloud

Analog/Custom Design

Balancing Analog Layout Parasitics in MOSFET Differential Pairs

Differential amplifiers apply gain not to one input signal but to the difference…

• 13 min read

Artificial Intelligence (AI)

Unraveling Generative AI Risks in Chip/System Design

When masterminds discuss ideas, possibilities, and perspectives, their collective…

• 7 min read
CadeneceLIVE , LLM , cadence.ai , Generative AI , ai-driven , GenAI , ai in eda , AI

Analog/Custom Design

Virtuoso Studio: Collaborate with the Right Intentions!

By Girish Vaidyanathan, Sr. Product Marketing Manager, Cadence Design Systems. The…

• 4 min read
collaboration , Virtuoso Studio , AMS Designer , Virtuoso , Layout design

Computational Fluid Dynamics

Women in CFD with Colinda Francke

We are excited to feature Colinda Francke, Senior Product Engineering Manager for…

• 7 min read
FidelityCFD , WomenAtCadence , women in engineering , engineering , simulation software , NUMECA , Women in CFD

Verification

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

In a landscape characterized by increasingly intricate designs and rapidly diminishing…

• 5 min read
Xcelium Logic Simulator , Multi-Core , best practices , verification

Digital Design

Joules RTL Design Studio: Accelerating Fully Optimized RTL

Cadence announced Joules RTL Design Studio today at CadenceLIVE Japan 2023, a new…

• 2 min read
digital design , RTL diff , featured , RTL synthesis , RTL restructuring , PPAC , Digital Implementation , lint checker , RTL design , RTL debugging , RTL analysis , Joules RTL Design Studio
CDNS - Fix Layout Hompage