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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Open Cavity Design Tools for IC Packaging Now Available in 16.6

In version 16.5 of the Cadence IC package layout tools, we introduced embedded discrete…

• 3 min read
IC Package , IC Packaging , packaging , open cavity , 16.6 , IC Packaging and SiP , Allegro Package Designer , Sigrity , APD 16.6 , SiP Layout , cavity

Verification

New Product: ARM ACE Assertion-Based Verification IP (ABVIP) Available Now

Preface: on Tuesday December 11 we are giving a free a webinar on "ACE Assertion…

• 1 min read
ACE , ABV , Joerg Mueller , ABVIP , Mirit Fromovich , ACE verification , ARM , AMBA4

Analog/Custom Design

SKILL for the Skilled: Part 5, Many Ways to Sum a List

In the most recent posts of SKILL for the Skilled (see previous post here ) we looked…

• 5 min read
Team SKILL , Jim Newton , summing , Virtuoso , Lisp , SKILL++ , sumlist , SKILL

Verification

Techniques to Boost Incisive Simulation Performance

Functional verification is the biggest challenge in delivering more complex electronic…

• 3 min read
performance , Accleration , simulation speed , Incisive Enterprise Simulator (IES)

Verification

UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented…

• 1 min read
AF , uvm , Specman , Functional Verification , vr_ad , Register Package , e language , UVMe , register enhancements

Verification

Optimizing ARM Based Designs for Low Power using Emulation

The month November goes to the Brits, no question. Not only did the James Bond movie…

• 5 min read
ESL Market , Nufront , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , Peng Wang , cadence , Acceleration , Functional Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Palladium XP , Emulation , ARM , Schirrmeister , low power optimization

RF Engineering

MMSIM 12.1 SpectreRF -- Preview of Coming nport Attractions! Part 2

Greetings, MMSIM 12.1 contains many new features to aid RF designers. Many of these…

• 2 min read
nport , RF , RF Simulation , analog/RF , Circuit simulation , Wilsey , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , nport settings , Virtuoso Spectre Simulator GXL , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , harmonic balance , simulation

Verification

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are…

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying…

• less than a min read
IEEE 1647 , Specman , Hannes Froehlich , Functional Verification , MOOC , Udacity , training , VA Partners , verification alliance , e language

Digital Design

The Case for the Tiny Testcase

I often joke with customers that, although I realize they have to work on large designs…

• 2 min read
debug , tiny testcase , testcase , Test , encounter , Digital Implementation , small testcase , test case , Bob Dwyer , verification

Analog/Custom Design

Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

Are you working in the area of mixed signal? Then you may want to exchange information…

• 1 min read
ITDB , mixed-signal training , Andreas Lenz , analog on top , CPF , Mixed-Signal , encounter , Virtuoso , mixed signal , mixed-signal forum , OpenAccess , forum , Cadence Community

Analog/Custom Design

Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical…

The recently concluded ARM TechCon 2012 , the annual event for ARM users (including…

• 2 min read
ARM Techcon , EDI , chipestimate , ARM Cortex M0 , AMS Designer , ARM Technology Symposium , 20nm , 14nm , Mixed-Signal , Virtuoso , mixed-signal book , Cortex-M0 , mixed signal , mixed-signal design , ARM , ARM-Cortex-M

Verification

CDNLive paper: High-level Synthesis on Video Processing ASIC

The proceedings from the recent CDNLive! event in Israel recently became available…

• 1 min read
High-Level Synthesis , video processor , Jack Erickson , CDNLive , System Design and Verification , Freescale , rtl compiler , C-to-Silicon , Israel , SystemC , CDNLive! , DAC 2012 , HLS , ESL

System, PCB, & Package Design 

What's Good About APD’s Shape Shorting? You’ll Need the 16.6 Release to See!

In some designsflows, you need to connect two plane shapes on the same net, but on…

• 5 min read
PCB , IC Packaging and SiP Design , blind vias , IC Packaging , Allegro GUI , inset vias , Allegro 16.6 , packaging , Digital SiP design , layer stacks , High Speed , shape shorting , APD , IC/package co-design , Allegro Package Designer , advanced package designer , via , design , vias , PCB design , Grzenia , shorting vias

Digital Design

Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

The trend of combining analog and digital circuits on a single chip has been growing…

• 4 min read
EDI system , LEF , Cadence Online Support , Mixed-Signal , encounter , Virtuoso , oa , Digital Implementation , PDK , mixed signal , LEF to OpenAccess , Brian Wallace , OpenAccess , blog

RF Engineering

MMSIM12.1 SpectreRF Preview of Coming Attractions! - Part 1

Greetings! MMSIM 12.1 contains many new features to aid RF designers. Here's a preview…

• 2 min read
RF , RF Simulation , analog/RF , envelope , Circuit simulation , Wilsey , shooting newton , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , ADE-L , Analog Simulation , MMSIM , fast envelope , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , RF design , harmonic balance

Verification

Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages…

• 2 min read
AF , Specman , function level , Functional Verification , C Interface , e language , Specman C , TCM , PLI

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Component Alignment? See for Yourself in 16

The Component Alignment feature is available in Placement Edit Application mode.…

• 1 min read
PCB , DFA , Allegro 16.6 , 16.6 , Placement Edit , Component Alignment , PCB Editor , PCB design , Grzenia , Spacing , Allegro PCB Editor , alignment , Allegro

Verification

Creating Custom File Systems and the Linux Loop Device

A few weeks ago we had a crisis at our house. My son managed to delete the data from…

• 7 min read
virtual platforms , Linux loop , File System , virtual prototypes , chroot , System Design and Verification , embedded software , Ubuntu , linaro , custom file systems , mount -o loop , ARM Architecture , Zynq virtual platform , linux , Jason Andrews , Zynq-7000 , simulation

Verification

How Many Cycles are Needed to Verify ARM’s big.LITTLE on Palladium XP?

At the recent CDNLive! India user conference, Deepak Venkatesan and Murtaza Johar…

• 5 min read
ESL Market , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , Functional Verification , System Design and Verification , big.LITTLE , System Development Suite , embedded software , Palladium XP , Emulation , ARM , cost of ownership
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