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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

Computational Fluid Dynamics, Software, and Chip Design

There are a lot of commonalities between computational fluid dynamics (CFD), software…

• 5 min read
CFD , computational software , EDA , software analysis

Life at Cadence

My Life at Cadence: Dajana Danilovic

Today’s interview features Dajana Danilovic, an application engineer based near Munich…

• 1 min read
Insights on Culture , cadence , GPTW , my life at cadence , LifeAtCadence , women in tech , great place to work , cadence emea

CFD（数値流体力学)

FINE /MARINE 10.2 国内公式リリース

FINE/Marine の最新バージョンでは、耐航性計算の高速化、抵抗計算の粗メッシュ初期化、Rhinoプラグインによるジオメトリ準備の高速化、解適合格子の改善などが行われています…

• less than a min read
CFD , naval archicture , Marine Engineering , automation , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software , japanese blog , Omnis , simulation

Computational Fluid Dynamics

This Week in CFD

Welcome, CFDers, to a new year of CFD news, applications, software, events, and general…

• 1 min read
CFD , Flashpoint , automotive engineering , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation , Omnis

Breakfast Bytes

Offtopic: Headlines

Monday is Martin Luther King Jr. Day. Breakfast Bytes will not appear and so today…

• 3 min read
offtopic

PCB設計／ICパッケージ設計

ASCENT: ブラウザベースのダッシュボードからSystem Captureの機能にアクセスする

エレクトロニクス設計のプログラムマネージャーやチームマネージャーであれば、Allegro® System Captureなどの設計ツールを直接使って仕事をすることはまずないでしょう…

• less than a min read
17.4-2019 , Allegro System Capture , japanese blog , ASCENT , 17.4-QIR3

Breakfast Bytes

Jasper User Group Best Paper 2021

The annual Jasper User Group was held in November. I've already written several posts…

• 8 min read
Jasper User Group , JUG , formal , ARM , JasperGold

PCB設計／ICパッケージ設計

IC Packagers: IC Package Designでの既製部品に関するサポート

Allegro® Package Designer Plusの17.4-2019 HotFix 019より前のバージョンでは、デザイン上でClassがICタイプの部品はすべてDie…

• 1 min read
APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , japanese blog

SoC and IP

Improving Performance and Throughput While Implementing FFT Using Tensilica ConnXB20…

Real-time FFT performance in Radar, Lidar, and ADAS applications is limited by data…

• 6 min read
DSP , cadence , tie , semiconductor IP , DIT , Tensilica IP , FFT

Breakfast Bytes

The State of the RISC-V Union, part II

This is part 2 of my post on DAC and RISC-V from December. The first post is here…

• 7 min read
risc-v , risc-v summit

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: Sigrity Xによる次世代シグナル/パワーインテグリティソリューション

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
Sigrity and Systems Analysis , Sigrity X , Power Integrity , Signal Integrity , japanese blog

PCB解析／ICパッケージ解析

System Analysis Knowledge Bytes: Layout Workbenchへ移行したSPEEDEM

System Analysis Knowledge Bytesブログシリーズでは、Cadence®が提供するシステム解析ツールの機能と可能性について説明しています…

• 1 min read
Sigrity and Systems Analysis , Clarity 3D Transient Solver , Power Integrity , Signal Integrity , japanese blog , Sigrity 2021.1 , Sigrity SPEEDEM , Layout Workbench

System, PCB, & Package Design 

Welcome to 2022: A World of Possibilities in IC Packaging!

Hello, everyone, and a happy new year! Last year was incredibly exciting for IC Packaging…

• 6 min read
17.4 , IC Packaging , APD , IC Packaging & SiP design , Allegro Package Designer , 17.4-2019

System, PCB, & Package Design 

(P)SpiceITUp: Using Monte Carlo to Make Sense of Randomness and Calculate Yield

Any circuit you design uses parts that will vary depending on many factors that are…

• 7 min read
OrCAD Capture , PSpiceA/D , (P)SpiceItUp , 17.4-2019 , PSpice Advanced Analysis

Breakfast Bytes

DAC...and the State of the RISC-V Union

Due to the pandemic, events that normally occur earlier in the year all piled up…

• 4 min read
DAC , risc-v , risc-v summit , semi , Design Automation Conference

Breakfast Bytes

CES 2022...in Person but Not Many People

CES was and is officially hybrid, with some events on-site in Las Vegas and some…

• 4 min read
Consumer Electronics Show , CES , ces 2022

The India Circuit

Mentor Story: Vivek B N - Cadence Scholarship Program

The Cadence Scholarship Program is the flagship CSR program of Cadence India, introduced…

• 2 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Breakfast Bytes

TSMC OIP: 3DFabric (Advanced Packaging)

At the recent 2021 TSMC OIP Ecosystem Forum, there were two special presentations…

• 4 min read
OIP , 3DIC , TSMC , soic

System, PCB, & Package Design 

ASCENT: Configuring Design Constraints the Easy Way

Constraint capture made easy with in-context editing right next to the circuitry…

• 3 min read
System Capture , 17.4 , Constraint Manager , 17.4-2019 , design , Constraints , ASCENT , Schematic , Allegro
CDNS - Fix Layout Hompage