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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Latest blogs

The India Circuit

Story of Leela Raghavan - Cadence Scholarship Program

Leela’s story unfolded in a corner of Bangalore—one of quiet strength, profound loss…

• 2 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India

Verification

High-Bandwidth Memory Evolution from First-Generation HBM to the Latest HBM4

HBM4 is the latest generation of the High Bandwidth Memory (HBM) that has become…

• 3 min read
Verification IP , VIP , JEDEC , HBM , hbm4 , DRAM , High Bandwidth Memory , memory models , HBM3 Vs HBM4 , verification

Digital Design

Race to First-Pass RTL: Improve PPA Targets Using Stratus HLS

Traditional RTL design methodologies often fall short in the race to deliver faster…

• 5 min read
High-Level Synthesis , online courses , Cadence training , Stratus , SystemC , online training , HLS , cadence learning and support

Computational Fluid Dynamics

Sailing Through the Waves of Competitive Racing with Fine Marine

Fine Marine's CFD tools enhance performance and efficiency in marine racing design…

• 5 min read
FINE Marine , Computational Fluid Dynamics , vendee globe , Mesh Generation , Americas Cup

中文技术专区

破局 AI 算力困局：3D-IC 技术架构的颠覆性变革

AI 时代的数据洪流与算力瓶颈 从日常生活中的语音助手和自动驾驶，到工业上的全自动工厂和 AI 辅助设计，人工智能技术正在为我们的世界带来革命性的变化。在人工智能的应用中…

• less than a min read
Integrity

SoC and IP

Rethinking AI Infrastructure: The Rise of PCIe Switches

Boring? Think Again. PCIe Switches Are the Hidden Power Behind AI When thinking of…

• 5 min read
controller IP , CXL , PCIe controller , Design IP , PCIe Gen4 , pcie4 , PCIe 7.0 , IP design , PCIe , future of IP , PCIe PHY , PCIe 6.0 , PCI Express

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Verification

Verification of PCIe's TDISP for Device Interface Security

The TEE Device Interface Security Protocol (TDISP) is a critical component in ensuring…

• 5 min read
Verification IP , Functional Verification , CXL3.0 , PCIe , TDISP , IDE , verification

System, PCB, & Package Design 

BoardSurfers: Training Insights: Learn RF Design with Allegro X RF PCB Course

The Allegro®︎ X RF PCB course offers a practical, one-day training for engineers…

• 3 min read
RF PCB , Allegro X PCB Editor , BoardSurfers , PCB Editor , PCB design , Training Insights , allegro x

System, PCB, & Package Design 

Join Cadence Community Super User Program

Join the Community Super User Program to share expertise, inspire peers, and grow…

• 1 min read
PCB , community forum , PCB design , CADENCEFORUMS

Corporate News

ICSense Designs ASICs for Next-Generation Medical Implants

ICsense is a leading supplier of application-specific integrated circuits (ASICs…

• 2 min read
spectre simulation , Virtuoso Studio , Xcelium Logic Simulator , designed with cadence , Voltus

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

• 1 min read
IC25.1 , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement , IC Release Blog , Custom IC Design , Cadence Community

SoC and IP

Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

As AI data centers continue to scale up and out to accommodate increasingly compute…

• 1 min read
PCIe controller , ucie , HBM , PCIe 7.0 , PCIe , DDR IP , UALink , PCIe 6.0 , PCI Express

Digital Design

Enhancing RTL Power Efficiency with xReplay, FlashReplay, and Clock Gating

Innovative Solutions for Power-Efficient RTL Design and Technology As semiconductor…

• 6 min read
digital badge , Low Power , Power-Efficient Design , Joules , training , training bytes , Power Analysis , online training , clock gating , RTL analysis

Verification

An Overview of CXL Mode Alternate Protocol Negotiation

The Peripheral Component Interconnect Express (PCIe) protocol has a very powerful…

• 4 min read
CXL , Verification IP , VIP , PCIe , verification

Corporate News

3D-ICs in the Automotive Market: Breaking Barriers with AI-Driven EDA Tools

The automotive industry is experiencing a significant transformation as it adopts…

• 6 min read
Automotive , chip design , 3D-IC , automotive electronics , integrity 3d-ic , indesign , jedai , AI

Life at Cadence

Restoring Nature, One Vine at a Time

Written by Shrini Farrahi A dedicated team of 30 Cadence volunteers recently came…

• 1 min read
Cadence Giving Foundation , giving back , LifeAtCadence , We Are Cadence , volunteering , One Cadence One Team

System, PCB, & Package Design 

Case Study: How to Sign Off Your UCIe Interface

As 3D heterogeneous integration (3DHI) systems increase in complexity, the importance…

• 3 min read
IC Packaging , Signal Integrity , Sigrity , SystemSI

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

• 4 min read
news story , featured , Cadence Academic Network
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