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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

カスタムIC／ミックスシグナル

Virtuoso Video Diary: 信頼性解析の改善

IC6.1.8/ICADVM18.1 ISR3のVirtuoso® ADE Assembler および Virtuoso ADE Explorer で、信頼性解析の実行方法を完全に変更する…

• less than a min read
Stress Analysis , Cadence blogs , ICADVM18.1 , ADE Explorer , Virtuoso Analog Design Environment , Virtuoso Video Diary , aging , japanese blog , reliability analysis , Custom IC Design , IC6.1.8 , ADE Assembler

Analog/Custom Design

Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE…

Post-Layout has become a hot topic recently. This has kept me and several other engineers…

• 2 min read
Analog Design Environment , PAD , ICADVM18.1 , ADE Explorer , Spectre , Virtuosity , Custom IC Design , IC6.1.8 , parasitics

Breakfast Bytes

HOT CHIPS: The Space Race for the Biggest ML Machine

At the recent HOT CHIPS, the Sunday morning tutorial was on scale out of deep learning…

• 5 min read
GPU , deep learning , tpu , NVIDIA , cerebras , wafer scale integration , google , training , mlperf

Verification

Mellanox's Tips and Tricks for Maximizing Your Palladium Unit

Looking to learn more about the best practices for emulating today’s billion-gate…

• 1 min read
Functional Verification , mellanox , Palladium , Tips

Breakfast Bytes

OIP Ecosystem Forum 2020

Last Tuesday was the virtual TSMC OIP Ecosystem Forum. Apart from being virtual,…

• 3 min read
OIP , Automotive , n5 , oip ecosystem summit , ultra low power , n3 , TSMC , 16FFC , n7 , n6 , n12e , 3dfabric

System, PCB, & Package Design 

BoardSurfers: Find by Name or Find by Query - That is the Question!

You must be using find utility day in and day out, but if you are unfamiliar with…

• 9 min read
Find command , APD , PCB Editor , FIND , Find result , Find by Query

System, PCB, & Package Design 

IC Packagers: Preparing a Completed Package for Mounting on a PCB

We’ve covered all the different types of die components and how they interface with…

• 5 min read
IC Packaging and SiP , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Andrew Kahng and Matthew Morrison on Industry and Academia

I attended two presentations on the academic track at the recent CadenceLIVE Americas…

• 6 min read
DAC , ucsd , academia , andrew kahng , physical design , notre dame , matthew morrison , HLS

定制IC芯片设计

Virtuoso Meets Maxwell: 当裸片版图没有Bump，有Pad Shapes时，怎么输出裸片版图?

如果您的裸片版图不是通过Bumps，而是通过 pad shapes和标签来识别I / O位置，那么您可能会有种无所适从的感觉。 因此在这篇文章中，我将为大家介绍一种新的适用于裸片版图的解决方案…

• 2 min read
Chinese blog , ICADVM18.1 , Edit-in-Concert , die export , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Layout EXL , Package Design in Virtuoso , die , virtuoso system design platform , shape-based die , shape , VMM

Analog/Custom Design

Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability…

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple…

• 3 min read
IC Packaging , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso Analog Design Environment , Virtuoso , Spectre , mixed signal , Custom IC Design , Allegro

Breakfast Bytes

Sunday Brunch Video for 6th September 2020

https://youtu.be/bj1-b3YpuXg Made in "Costa Rica" Monday: Cadence Wins Texas Instruments…

• less than a min read
sunday brunch

カスタムIC／ミックスシグナル

Virtuosity: 日本の読者に朗報です

最近私たちは、ノートパソコン、スマートフォン、テレビなど、画面の前でほとんどの時間を費やしています。 これらのガジェットは、自宅やオンライン・プロジェクト、その他の仕事関連のタスクでの作業を簡単にサポートする…

• 1 min read
Trunk generation , ICADVM18.1 , AMS Designer , VPR , Advanced Node , layout XL , Virtuoso , Virtuosity , AMSD Flex Mode , japanese blog , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

Labor Day Offtopic: Microroasting Coffee

Labor Day is coming up on Monday. Friday is also a Cadence holiday and Breakfast…

• 6 min read
offtopic , off topic , coffee

PCB設計／ICパッケージ設計

inspectAR: ニューファンドランドの”拡張現実”（AR）

先日、CadenceLIVEでのAnirudhの基調講演について Anirudh's Keynote: A New Product...and an Acquisition…

• less than a min read
PCB , inspectar , japanese blog

System, PCB, & Package Design 

BoardSurfers: Implementing SKILL Code

This post is in continuation of  Extending Allegro Layout Capabilities with SKILL…

• 2 min read
17.4 , PCB design and layout , 17.4-2019 , PCB design , Allegro PCB Editor , SKILL

Breakfast Bytes

CadenceLIVE India 2020 Preview

In a normal year, I would already have my plane ticket to fly to Bangalore for CadenceLIVE…

• 3 min read
cadencellive india , cadencelive

Verification

Xcelium ML: The Next Big Thing in Regression

Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic…

• 1 min read
machine learning , xcelium , Regression

System, PCB, & Package Design 

IC Packagers: How Die Stacking Works in Allegro Package Designer

Recently, we’ve covered some basics about why imported dies default to chip-down…

• 7 min read
IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

InspectAR: Augmented Reality in Newfoundland

I covered Anirudh's CadenceLIVE keynote in my post Anirudh's Keynote: A New Product…

• 3 min read
PCB , inspectar , augmented reality
CDNS - Fix Layout Hompage