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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

TSMC’s Technology Symposium 2016 is the Place to be for Innovation

At this year’s Technology Symposium, TSMC disclosed that they will provide two N7…

• less than a min read
DDR4 , LPDDR4 , TSMC Tech Symposium , ip cores , PCIe , 16FF+

Breakfast Bytes

EDPS: Dolphins and FinFETs

The Electronic Design Process Symposium (EDPS) has been held in late April or early…

• 3 min read
Low Power , Electronic Design Process , multi-die , Monterey , EDPS , cyber security

Academic Network

Stratus High-Level Synthesis Is Available to Academia

To support academia using the latest industry-standard tools, Cadence's Stratus High…

• 1 min read
Cadence Academic Network , academia , Stratus , HLS

Breakfast Bytes

TSMC Technology Symposium: Process Status

At the recent TSMC Technology Symposium, various speakers gave details of the various…

• 6 min read
Automotive , specialty processes , IoT , TSMC , <7nm , InFO , 16FFC , n7 , n10 , Breakfast Bytes , 16FF+

Academic Network

Tensilica Day in Hanover

The idea to have a Tensilica Day at University of Hanover was born during CDNLive…

• 2 min read
Cadence Academic Network , Tensilica

SoC and IP

DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps

Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY…

• 1 min read

Breakfast Bytes

TSMC Technology Symposium: Four Strategic Markets

When Willie Sutton was asked by the judge why he kept robbing banks, he said "because…

• 3 min read
Automotive , IoT , TSMC , TSMC Technology Symposium , 7ff , 16ff , 10FF , 16nm , HPC , n7 , mobile , n10 , 7nm , 10nm , n16

Breakfast Bytes

Dark Silicon: Not a Character from Star Wars

Dark Silicon may sound like a character from the latest Star Wars movie, but it actually…

• 6 min read
Dennard scaling , Dark Silicon , moore's law , dennard , multicore

Breakfast Bytes

EDAC Becomes...You Have to Be There to Be the First to Know

When Bob Smith took over as the Executive Director of EDAC, I called him up and one…

• 2 min read
bob smith , EDA Consortium , EDAC , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—Implementation of Higher Speed PCIe Gen4 IP

In this week's Whiteboard Wednesday's video, Gopi Krishnamurthy highlights how Cadence…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PHY IP , PCIe , PCI Express

Breakfast Bytes

The Economist on the End of Moore's Law

"The number of people predicting the end of Moore's Law doubles every two years.…

• 3 min read
Intel , The Economist , moore's law , FinFET

Breakfast Bytes

A Brief History of Cadence: The Solomon-Costello Era

Cadence has grown from a small startup to a $1.7B corporation. Its history includes…

• 3 min read
Jim Solomon , ECAD , Joe Costello , SDA

System, PCB, & Package Design 

Designing a New Component from Scratch Inside Your Layout Environment

Have you ever needed to build a component with a custom, complex pin pattern? Have…

• 6 min read
IC package design , APD , package design , Allegro Package Designer , SiP Layout , substrate design tools

Breakfast Bytes

Tensilica Has Its Own Track at CDNLive Silicon Valley

Tensilica products are a bigger business than many people realize. The product line…

• 2 min read
IP , CDNLive , processor , Tensilica , Xtensa , DSPs

Breakfast Bytes

DVCon Keynote: the Past and Future of Verification

Last week was DVCon, the design and verification conference. Despite the D standing…

• 5 min read
SystemVerilog , Wally Rhines , formal , Verilog , Emulation , DVcon , Rhines , simulation , verification

Breakfast Bytes

EDA in the Cloud: Stormy Weather

SoC design groups don't do clouds. True, they take advantage of some of the underlying…

• 4 min read
security , EDA , cloud , Breakfast Bytes , cloud computing

Whiteboard Wednesdays

Whiteboard Wednesdays - Reusable Data-Driven Verification Using TLM 2.0

In this week's Whiteboard Wednesdays, Zeev Kirshenbaum describes a method for creating…

• less than a min read
SystemVerilog , Verification IP , Whiteboard Wednesdays , TLM 2.0 , data driven verification

System, PCB, & Package Design 

What's Good About the Latest PSpice? The 16.6-2015 Release Has Several New Enhancements…

The 16.6-2015 PSpice release has several new features and capabilities: VBIC Support…

• 2 min read
Allegro 16.6 , AMS simulator , 16.6 , PSPICE , PCB design , AMS simulation , Grzenia

Breakfast Bytes

Turing Award; Google's First Crash

Turing Award 2016 The highest award in computer science, sometimes referred to…

• 3 min read
rsa , public key cryptography , turing award , google car , cryptography , turing , alan turing , diffie helman
CDNS - Fix Layout Hompage