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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Verification

Training Insights – VHDL Language and Application

Cadence has released a new online VHDL training course free for Cadence Customers…

• 2 min read

Computational Fluid Dynamics

On-Demand Webinar: Making the Shipping Sector Greener by Leveraging CFD

CFD tools have become commonplace to optimize vessel design and reduce lifetime fuel…

• less than a min read
CFD , Marine Engineering , shipping , FINE Marine , featured , marine design , naval architecture , marine , Computational Fluid Dynamics , webinar , fluid dynamics , CFD Applications , Cadence CFD , naval

RF Engineering

Knowledge Booster Training Bytes - The Close Connection Between Schematics and Their…

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing…

• 1 min read
RF , RF Simulation , RF designer , AWR customization , RF design , microwave office

Breakfast Bytes

Offtopic: Thanks

Happy New Year! Normally, as you will know if you are a regular reader of Breakfast…

• 8 min read
offtopic , Thanks

Computational Fluid Dynamics

Defining a Good Grid for Solution Accuracy

CFD practitioners must decide on several simulation aspects, such as solution algorithms…

• 5 min read
Mesh quality metrics , Meshing Monday , advection , Computational Fluid Dynamics , Solution Accuracy , engineering , simulation software , Cadence CFD , Meshing , Fidelity Pointwise

Breakfast Bytes

Sunday Brunch Video for 25th December 2022

https://youtu.be/V2368Zo4Tb4 Direct link if it says the video is blocked, Made…

• less than a min read
Breakfast Bytes

カスタムIC／ミックスシグナル

Virtuosity: ViVA XLでのシングル・ポイント・シミュレーションのスカラー出力のアノテーション

私たちは、製品を使いやすくすること、簡単にアクセスできるようにすること、視覚的に魅力的であることがユーザビリティの考え方であると言われている世の中に生きています…

• less than a min read
annotation , Scalar Outputs Annotation , ADE Explorer , Summary Label , Virtuoso Visualization and Analysis XL , Virtuoso Analog Design Environment , ViVA , Virtuosity , Single Point Simulation , japanese blog , ISR26 , Scalar Ouputs , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler

Life at Cadence

Honda Is Replacing Their Manual Meshing Processes with Cadence CFD

When it comes to cars, motorcycles, and power equipment, Honda is a household name…

• 1 min read
CFD , designed with cadence , fidelity , NUMECA , Omnis , Honda

Life at Cadence

LPDDR5X: Why Mobile Memory Matters More than Ever

Since its ratification in the mid-2000s, low-power DDR (LPDDR) has been fundamental…

• 5 min read
featured , lpddr5x , Denali

Breakfast Bytes

Cadence's DDR Portfolio...and LPDDR5X-8533

At the recent CadenceLIVE Europe, Marc Greenberg presented Cadence's portfolio of…

• 5 min read
ddr5 , Memory , featured , DRAM , lpddr5 , DDR

Digital Design

Voltus Voice: Dulce Domum and Happy Holidays!

A recap of the power integrity posts in the Voltus Voice blog series through 2022…

• 5 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , Power-Efficient Design , hierarchical power integrity analysis , Thermal Integrity , Power Analysis , vector profiling , vectorless

System, PCB, & Package Design 

The Year That Was: Cadence PCB & Package Design Blogs and Videos in 2022

Another year has gone by, and we continue to evolve with the new normal, inching…

• 1 min read
BoardSurfers , 22.1 , (P)SpiceItUp , PSPICE , IC Packagers , Allegro Package Designer , 17.4-2019 , Training Insights , Allegro System Capture , Allegro PCB Editor , ASCENT , Allegro

Digital Design

Voltus Voice – How to Step Up Your Game with Target Power Vectorless Dynamic EMIR…

Check out this blog to learn how you can perform accurate modelling of localized…

• 5 min read
Voltus IC Power Integrity Solution , Power Target Vectorless EMIR , Power Integrity , Power-Efficient Design , Digital Implementation , Power Analysis , signoff , vectorless , dynamic power

Breakfast Bytes

December Update: Chenming Hu, Leap Seconds, Right to Repair, and More

Cadence will be shut down on the last Friday in December, so despite this being only…

• 7 min read
transistors , Apple , update , power , right to repair

Computational Fluid Dynamics

On-Demand Webinar: LMG Marin Cuts Time and Costs in Ship Design Using Fine Marin…

LMG Marin is a naval architecture design and engineering office working on commercial…

• 1 min read
CFD , Marine Engineering , marine design , webinars , marine , fine/marine , Computational Fluid Dynamics , fluid dynamics , CFD Applications , simulation software

Computational Fluid Dynamics

Women in CFD with Fanny Besem-Cordova

For the December post of the Women in CFD series, we have Fanny Besem-Cordova, principal…

• 6 min read
CFD , Pointwise , fluid dynamics , WomenAtCadence , Fidelity CFD , women in engineering , simulation software , NUMECA , Women in CFD

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: パッケージ・レイアウトからパッケージ回路図を自動生成できるのですか？

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
IC Packaging , Footprint , VRF , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF Solution , Virtuoso MultiTech , Package Design in Virtuoso , Virtuoso , RF design , japanese blog

Analog/Custom Design

Knowledge Booster Training Bytes – Place and Route Using Virtuoso Placer

Do you know you can do placement of the devices by using Virtuoso Placer, which helps…

• 6 min read
Advanced Node , Virtuoso Placer , analog/mixed-signal , Custom IC Design , Virtuoso Layout Suite EXL , Row-Based Placement

Breakfast Bytes

RISC-V Summit Day 2: Krste, Android

My first post about the recent RISC-V Summit appeared last week: RISC-V Summit 2022…

• 4 min read
risc-v , featured , risc-v summit , risc-v foundation
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