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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

CFD: It's More Than an Acronym - Learn More at CadenceLIVE

Excuse me, sir. Are you lost? That's what you might be thinking. Why is this guy…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , NUMECA

Breakfast Bytes

Countdown to TSMC Technology Symposium: 7nm, 5nm, 3nm, June 1

Today it is the TSMC 2021 Online North America Technology Symposium (tomorrow for…

• 3 min read
n4 , n3 , TSMC , TSMC Technology Symposium , custom/analog flow , digital full flow

Analog/Custom Design

Virtuoso Meets Maxwell: Defining Ports in EMX Planar 3D Solver

Fast and accurate electromagnetic simulation is becoming critical in a growing number…

• 6 min read
VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , EMX , EM Analyis , RF design , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL

PCB、IC封装：设计与仿真分析

如何在IC封装设计中告别锐角问题？

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年…

• less than a min read
PCB , IC , Chinese blog , 17.4 , APD , Allegro Package Designer Plus , PCB设计 , 中文 , IC封装 , 锐角 , Allegro

Digital Design

Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

In the concluding blog of our "Demystifying ESD" series, we walk you through the…

• 6 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , ESD reports , electrostatic discharge , current density , Power Integrity , Innovus , clamp , bump

Digital Design

SSV 21.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download…

• 3 min read
Celsius Thermal Solver , Temperature Map , Voltus IC Power Integrity Solution , 3nm , Power Integrity , Power Targets , silicon signoff , Tempus Timing Signoff Solution , Extreme Modeling

Breakfast Bytes

Offtopic: "Pole Pole" to the Top of Kilimanjaro

Today is the last blogging day before Memorial Day on Monday, so as is now traditional…

• 8 min read
offtopic

Computational Fluid Dynamics

Fluid Dynamics Investigation of the Sonic Boom on a Supersonic Aircraft

The return to supersonic flight is amongst the hottest topics in aviation today,…

• 1 min read
CFD , Aerospace , Computational Fluid Dynamics , fluid dynamics , NUMECA , Omnis

Breakfast Bytes

Why Attend CadenceLIVE Americas 2021 on June 8 and 9?

Once again this year, CadenceLIVE Americas is coming up soon and it will be completely…

• 6 min read
cadencelive americas , cadencelive

Analog/Custom Design

Virtuosity: Learn the Right Steps—Design 5G Your Way with Cadence Training

In this blog we would like to let you know – amongst other things - how to implement…

• 3 min read
5G , Virtuoso RF , training , Cadence training , digital badges , Virtuoso , Cadence certified , Virtuoso Video Diary , Custom IC Design , online training

定制IC芯片设计

Virtuoso Video Diary: “Training Bytes” 助推知识传播—第5部分

2021年Knowledge Booster 系列博客，我们将介绍如何修改相关参数来解决Spectre Simulation DC的收敛问题和报错问题。

• 3 min read
blended , Chinese blog , Spectre DC , Spectre Pro , training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Cadence Education Services , Custom IC Design , online training

Analog/Custom Design

Spectre Tech Tips: Introducing Spectre Analog Fault Analysis

Chip tests have become more demanding as defects tend to occur more often in scaled…

• 3 min read
onestep , fault analysis , DFA , timezero , opens , bridges , maxiters , custom faults , direct fault analysis , spectre_fsrpt , faultleadtime , tfa , spectre_ddmrpt , parametric faults , linear , transient fault analysis , detection matrix

Breakfast Bytes

Bringing Clarity to the Cloud

Cadence announced Clarity 3D Solver Cloud as part of Cadence Hybrid Cloud, providing…

• 5 min read
Analog Design Environment , system analysis , ADE , clarity cx , Spectre , cadence cloud , hybrid cloud , Clarity 3D Solver , clarity

System, PCB, & Package Design 

IC Packagers: Analyzing and Fixing Wire Bond-Specific Design Issues

Design reuse is the key to faster design cycles in today’s packaging design industry…

• 3 min read
17.4 , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , wirebonding

Computational Fluid Dynamics

Tutorial Tuesday - It's Time to Learn Some Meshing

Today's not just Tuesday, it's Tutorial Tuesday. What's that, you ask? Each Tuesday…

• less than a min read
CFD , video , Pointwise , tutorial , Computational Fluid Dynamics , Mesh Generation , Meshing

Breakfast Bytes

Rapid Adoption Kits for Arm's Premium Mobile Platforms

Today, Arm announced its new lineup of processors for mobile. These are the first…

• 4 min read
Rapid Adoption Kit , RAK , digital full flow , mobile , verification full flow , ARM

System, PCB, & Package Design 

BoardSurfers: Managing Minor Spacing DRCs Using Manufacturing Tolerances

While translating boards from different PCB design applications or changing design…

• 2 min read
17.4 , BoardSurfers , EDA , PCB Editor , 17.4-2019 , Allegro PCB Editor , Allegro

SoC and IP

Introducing Cadence IP for PCIe 6.0

Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous…

• 3 min read
controller IP , CXL , Design IP , IP , PHY , PCIe , semiconductor IP , SerDes , PCIe 6.0 , PCI Express

Breakfast Bytes

PCIe 5.0 and 112G-LR IP in TSMC N5

Well, that's a lot of tech gobbledegook in the title of this post. Here's what it…

• 3 min read
pcie version 5 , 112G-LR , PCIe , 112g , SerDes , PCI , PCI Express
CDNS - Fix Layout Hompage