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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
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Blog - Post List

Latest blogs

Life at Cadence

Empowered to Support Our Community

Cadence understands that the success of our business, our employees, and the community…

• 2 min read
Insights on Culture , giving back , Fortune 100 best companies to work for , great place to work

Verification

New Training Bytes Available Now: All About SystemVerilog Classes

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking…

• 2 min read
SystemVerilog , Functional Verification , classes , training , training bytes

Breakfast Bytes

IEDM: Embedded Memories

On the Sunday of IEDM are two short courses, one memory-focused, and one logic-focused…

• 6 min read
Memory , deep learning , eflash , flash , envm , RRAM , MRAM , PCRAM , edram

Breakfast Bytes

Sunday Brunch Video for 27th January 2019

https://youtu.be/1gxIy7TGg3c Made at EBC (camera Sean) Tuesday: DesignCon: The Integrity…

• less than a min read
DesignCon , bletchley park , Amazon , gsa , dan niles

PCB、IC封装：设计与仿真分析

Cadence Sigrity 邀您莅临DesignCon 2019

时间：1月29-31日 地点：Santa Clara Convention Center，美国加州 Cadence诚邀您莅临DesignCon #711 展台，了解如何利用Cadence…

• less than a min read
SI , PI , Chinese blog , 电源完整性 , DesignCon , Multi-Gigabit , IC封装设计 , 光电设计 , 高级封装 , IBIS-AMI , 中文 , SerDes , DDR , Sigrity , 信号完整性

Breakfast Bytes

Amazon Go: Just Walk Out Shopping

Last year you probably heard about Amazon Go when it opened in Seattle. This is a…

• 3 min read
amazon go , mobile , Amazon , whole foods

Analog/Custom Design

Spectre Tech Tips: Optimizing Spectre APS Performance

This blog discusses how to optimize the Spectre APS performance for analog and mixed…

• 14 min read
spectre aps , Circuit simulation , ADE Explorer , simulation performance , Simulation Accuracy , Spectre XPS MS , ADE , Spectre Tech Tips , Spectre

Breakfast Bytes

"The First Half of 2019 Is Likely to Be Really Bad"

The title of this post was the single line summary of Dan Niles' quarterly outlook…

• 5 min read
capex , niles , Semiconductor , mobile , gsa

Breakfast Bytes

Why the Nation That Invented the Computer Lost Its Lead

Last month I wrote about a piece that Lynn Conway wrote for IEEE Computer Magazine…

• 9 min read
colossus , bletchley

Breakfast Bytes

DesignCon: The Integrity Show

It's the end of January and that means DesignCon. It is January 29th to 31st in the…

• 3 min read
PCB , DesignCon , Power Integrity , silicon photonics , Signal Integrity , photonics , Sigrity

The India Circuit

A Boost For Fabless Chip Design in India

There was a lot of excitement when the National Policy on Electronics was announced…

• 3 min read
National Policy on Electronics , entrepreneurship , Electropreneur Park , SFAL , FabCi , ESDM , npe

Breakfast Bytes

Sunday Brunch Video for 20th January 2019

https://youtu.be/Bs5A09med6Q Made at the Cadence campus in the rain (camera Sean…

• less than a min read
alphazero , CES , AMD , Tensilica , EUV , IEDM

PCB、IC封装：设计与仿真分析

了解DDR5技术之前需要知道什么是AMI与IBIS

本文翻译自Cadence "Breakfast Bytes"专栏作者Paul McLellan文章" AMI and IBIS: Who Put the Eye…

• less than a min read
Chinese blog , ddr5 , DDR4 , AMI , equalization , 均衡 , IBIS , 中文 , SerDes , Sigrity

Breakfast Bytes

MLK Off-topic: The Lady with the Polar Chart

It's Martin Luther King day on Monday, and Cadence is off. I think that this is the…

• 5 min read
offtopic , florence nightingale , statistics

System, PCB, & Package Design 

Cadence Sigrity at DesignCon 2019

Happy new year! We want to invite you to visit us in booth 711 on the DesignCon…

• 1 min read
SI , PI , electronics/photonic design automation , DesignCon , Multi-Gigabit , Advanced IC packaging , Power Integrity , IC package design , IBIS-AMI , DesignCon 2019 , Signal Integrity , SerDes , DDR , Sigrity

Analog/Custom Design

Virtuosity: What's New in Run Plan – Part III

After two interesting blogs by Yagya Mishra that explained the most popular features…

• 3 min read
Analog Design Environment , ICADVM18.1 , Rapid Adoption Kit , ADE , worst case corners , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , Run Plan , Custom IC Design , RAKs , IC6.1.8 , ADE Assembler

定制IC芯片设计

Virtuoso视频日记：这根线是怎样连接的？

Virtuoso Schematic Editor L 的Probes工具是连接辅助工具，能满足您识别已存在的连接关系，过滤这些连接关系，并且将探测路径信息存为CSV文件…

• less than a min read
Chinese blog , Virtuoso Schematic Editor , Virtuoso Video Diary , Probes assistant , Net Connections , Custom IC Design

Breakfast Bytes

IEDM: EUV, the Road to HVM and Beyond

At IEDM in December, the Sunday preceding the conference proper consists of two short…

• 8 min read
asml , EUV , IEDM

Breakfast Bytes

AlphaZero: Four Hours to World Class from a Standing Start

Last year I wrote about AlphaZero in my post Deep Blue, AlphaGo, and AlphaZero .…

• 7 min read
deep learning , alphazero , go , AI , stockfish , chess
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