Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

IEDM and RISC-V Summit 2022 Previews

There are two big events coming up in the first couple of weeks of December. IEDM…

• 5 min read
risc-v , risc-v summit , IEDM

Verification

Demystifying PCIe Lane Margining Technology

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology…

• 3 min read
Verification IP | Functional Verification | VIP | System Verification | simulation | verification

Breakfast Bytes

Cadence, McLaren, and the United States (Austin) Grand Prix

As you probably know, Cadence has a technology partnership with McLaren racing. I…

• 5 min read
CFD , F1 , mclaren , formula 1

Life at Cadence

Building Confidence through the Cadence Returnship Program

Re-entering the high-tech field after taking a break to prioritize family can be…

• 1 min read
Cadence Culture , returnship

System, PCB, & Package Design 

Cadence OrCAD and Allegro 22.1 is Now Available

The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads . This…

• 6 min read
TopXp , Cadence Design Systems , Sigrity Aurora , PSpiceA/D , 22.1 , PSPICE , Topology Explorer , PCB design , Allegro System Capture , Allegro PCB Editor , Pulse , Allegro

Life at Cadence

IQM Is Building the Next Generation of Quantum Computers

IQM seeks to solve one of the greatest technological challenges globally: building…

• 1 min read
RF , awr , designed with cadence

Life at Cadence

RISC-V Is Thriving – Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley…

• 4 min read
risc-v

Breakfast Bytes

Latinx Heritage Month

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage…

• 2 min read
latinx , latinx heritage month , Hispanic

Analog/Custom Design

Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Design Capture and Packaging (DCP) utility lets you isolate, capture and package…

• 5 min read
mixed signal design , AMS Designer , AMSD , Start Your Engines , Mixed-Signal , Design Capture , Cadence Community

Digital Design

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

• 3 min read
Stratus HLS , Genus

Computational Fluid Dynamics

Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level…

• 4 min read
openeye scientific , molecular sciences , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Cadence CFD , drug delivery mechanism

カスタムIC／ミックスシグナル

Spectre Tech Tips: ダイナミック電流密度チェック

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります…

• 1 min read
spectre aps , Spectre 21.1 , Dynamic Checks , Dynamic design checks , Spectre Circuit Simulator , Spectre , japanese blog , spectre x

Verification

USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This…

• 2 min read
USB4 VIP , USB4v2 , usb4 , USB4 Version 2

Computational Fluid Dynamics

Last Week at Fidelity CFD

It's Monday and time to look back on what happened last week here at Cadence Fidelity…

• 3 min read
CFD , turbomachinery , webinars , Pointwise , Computational Fluid Dynamics , fluid dynamics , Fidelity CFD , Mesh Generation

Computational Fluid Dynamics

On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor…

• less than a min read
CFD , Automotive , external aerodynamics , automotive engineering , featured , Computational Fluid Dynamics , fluid dynamics , simulation software , Aerodynamics

Digital Design

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

• 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Life at Cadence

Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Understand the role that density and compact design optimization play when designing…

• 5 min read
F1 , optimization , density , formula 1

Breakfast Bytes

USB-C – The Least Standard Standard Ever

In a post in our verification blog , Neelabh Singh told us that USB4 Version 2.0…

• 3 min read
usb 4.0 , USB , USB-C

Verification

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck
CDNS - Fix Layout Hompage