Cadence Blogs

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate 23 Jun 2026 • 3 min read

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate 22 Jun 2026 • 8 min read

featured , physical ai , HGR , AI , Honda

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate 22 Jun 2026 • 2 min read

featured , customer support , New ASK Portal , ASK Gen AI

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate 18 Jun 2026 • 7 min read

featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

cdns - all_blogs_categories

All 6412
Corporate News 264
Life at Cadence 204
Academic Network 169
Analog/Custom Design 804
Artificial Intelligence 27
Cloud 23
Computational Fluid Dynamics 374
Data Center 59
Digital Design 458
Learning and Support 62
RF Engineering 116
SoC and IP 435
System, PCB, & Package Design 1015
Verification 1326
Cadence Japan 18
Physical Systems Simulation 23

CFD（数値流体力学) 45
中文技术专区 9
カスタムIC／ミックスシグナル 199
PCB、IC封装：设计与仿真分析 136
PCB解析／ICパッケージ解析 44
PCB設計／ICパッケージ設計 61
RF /マイクロ波設計 45
Spotlight Taiwan 64
The India Circuit 93
定制IC芯片设计 79
データセンター 7

Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

PCB、IC封装：设计与仿真分析

如何在IC封装中连通晶片与球栅阵列封装（BGA）？

本文作者：Tyler Lockman，Cadence Software Architect，于加拿大卡尔顿大学获计算机科学学士学位后，在Cadence Allegro产品部门工作超过20年…

TeamAllegro 30 Oct 2020 • less than a min read

PCB , Chinese blog , 17.4 , Allegro Package Designer Plus , PCB设计 , 中文 , 17.4-2019 , IC封装 , Allegro

EPROM: Chips with Windows

I like to do the (London) Times crossword most days. For more information on how…

Paul McLellan 30 Oct 2020 • 6 min read

eprom , eeprom

カスタムIC／ミックスシグナル

Start Your Engines: AMS DesignerとSystemVerilogネットリスタ・フロー用HDL Packageを便利に定義するためのG…

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

Custom IC Japan 30 Oct 2020 • less than a min read

SystemVerilog , Virtuoso-AMS , mixed signal design , HDL Package , AMS Designer , japanese blog

Virtuosity: Conserve Power—A Preamble to Virtuoso Power Manager

Power consumption has always been an overriding concern in electronic design. Consumption…

deeptig 29 Oct 2020 • 4 min read

Virtuoso Schematic Editor , virtuoso power manager , clp , Virtuoso Schematic XL , Conformal Low Power , Mixed-Signal , VPM , Virtuoso , Virtuosity , ICADVM20.1 , Custom IC

Life at Cadence

Why I Loved Being a Technical Communications Intern at Cadence!

Through this blog, I share my experiences as an intern Technical Communications Engineer…

Rupesh Mainali 29 Oct 2020 • 6 min read

Permanent Employee , Cadence Cares , Technical Communications , intern , CPG , EDA , Cadence India , CSR , Technical Communications Engineer , internship

Jasper User Group: The State of Formal in 2020

Last week was the CadenceCONNECT: Jasper User Group conference. Of course, it was…

Paul McLellan 29 Oct 2020 • 6 min read

Amazon Web Services , formal , aws , cadence cloud , JasperGold , Formal verification

カスタムIC／ミックスシグナル

Virtuoso Video Dairy : Virtuoso Visualization and Analysis XL のDirect Measuremen…

プロットや波形の単純な測定値を作成するためだけに長い式を使用したり、振幅、立ち上がり、立ち下がり時間を測定するためにマーカーを使用したりしなければならなかったことはありませんか…

Custom IC Japan 29 Oct 2020 • less than a min read

Analog Design Environment , ViVa-XL , Virtuoso Analog Design Environment , Virtuoso , ViVA , japanese blog

System, PCB, & Package Design

BoardSurfers: Installation Know-How: Installing Cadence OrCAD and Allegro Products…

Often organizations do not grant administrative privileges to users on their systems…

Shikha Jain 28 Oct 2020 • 3 min read

17.4 , Allegro OrCAD Installer , 17.4-2019 , OrCAD , Allegro

Spectre Tech Tips: The Value of Spectre X in EMIR Analysis

EMIR analysis is one of the more challenging fields of circuit simulation. It requires…

Stefan Wuensche 28 Oct 2020 • 5 min read

Spectre X EMIR , EMIR Analysis , MX mode , Direct Method , Spectre , Iterated Method , spectre x

GDDR6 and HBM2E on Samsung Foundry — the SAFE Choice

Today is the Samsung SAFE forum. SAFE stands for Samsung Advanced Foundry Ecosystem…

Paul McLellan 28 Oct 2020 • 3 min read

Verification IP , IP , gddr6 , Samsung , hbm2 , hbm2e

Academic Network

System Design and Verification Training Deep Dive: Part 2

As we continue this blog series, we’re going to keep looking at System Design and…

Kira Jones 27 Oct 2020 • 4 min read

Europractice , Cadence Academic Network , System Design and Verification , CMC Microsystems , online training , university program

System, PCB, & Package Design

IC Packagers: Controlling Voids around Critical Signals

With greater and greater counts of high-speed and differential pair signals in designs…

Tyler 27 Oct 2020 • 5 min read

IC Packaging and SiP , Allegro Package Designer , 17.4-2019

Virtuoso Video Diary: Usability Enhancements in Digital Signals

Read through this blog to know more about the usability enhancements made to digital…

Udit Rajput 27 Oct 2020 • 3 min read

Mnemonic Map , Cadence blogs , ICADVM18.1 , simvision , analog , Virtuoso Visualization and Analysis XL , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuoso Video Diary , ICADVM20.1 , Configure Mnemonics , usability , Custom IC , IC6.1.8

CadenceLIVE Israel 2020 Preview

Coming up on November 3 is CadenceLIVE Israel. Google tells me that date is 16 Heshvan…

Paul McLellan 27 Oct 2020 • 3 min read

cadencelive , cadencelive israel

カスタムIC／ミックスシグナル

日本語版データシートの一覧はこちら！

ケイデンス製品をご利用のみなさま、そして、これからご利用を検討されるみなさま、先日はCadenceLIVE 2020 Japanにご参加いただき、ありがとうございました…

Custom IC Japan 26 Oct 2020 • 1 min read

legato , EAD , Virtuoso Schematic Editor , Virtuoso Variation Option , ADE Explorer , Virtuoso Multi-Mode Simulation , Spectre RF , Co-Analysis , Legato Reliability Solution , Co-Design , Analog Simulation , MMSIM , Legato Memory Solution , ADE , analog verification , Electorically Aware Design , Monte Carlo analysis , Virtuoso Analog Design Environment , virtuoso system design platform , Virtuoso , EMX , Spectre , ViVA , EMX Planner 3D Simulator , japanese blog , spectre x , Custom IC Design , Virtuoso Layout Suite , Custom IC , ADE Verifier , ADE Assembler