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Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

IC Packagers: Materially Good Changes in 17.4

You should be getting used to the new 17.4 release at this point. I am willing to…

• 4 min read
17.4 , APD

System, PCB, & Package Design 

BoardSurfers: Installing on Windows is as Easy as Updating Apps on your Smart Ph…

Did you know that you can download and install available Cadence Allegro and OrCAD…

• 1 min read
17.4 , install , 17.4-2019 , Download Manager , OrCAD , Allegro

Analog/Custom Design

Virtuosity: Sharing Expressions between Pre- and Post-Layout Simulations

This has been an age old problem, you extract your design and get a DSPF file, then…

• 2 min read
ADE Explorer , Rapid Adoption Kit , DSPF , ADE , postlayout , Custom IC Design , ADE Assembler

PCB、IC封装：设计与仿真分析

版本升级：Sigrity 2019、Allegro/OrCAD 17.4现已发布

space Sigrity 2019主要性能升级 新系统级分析工具：Celsius Thermal Solver 系统级电热协同仿真 Sigrity 2019版本引入Cadence…

• 1 min read
PCB , Chinese blog , SPB 17.4 , Sigrity 2019 , PSPICE , 中文 , OrCAD , 软件升级 , Sigrity , Allegro

Breakfast Bytes

Implementing Arm Hercules with Digital Full Flow

At Arm TechCon, there was a joint presentation by Arm, Cadence, and Samsung Foundry…

• 3 min read
Genus , hercules , Samsung , Innovus , ARM , full flow

Digital Design

Library Characterization Tidbits: Basics of Standard Cell Characterization and M…

Characterization of standard cell libraries using the Liberate Characterization solution…

• 2 min read
tidbits , SPICE netlist , Standard Cell , characterization , Liberty Files , Spectre , Library Characterization Tidbit , Digital Implementation , Characterization Solution , Liberate , Inside-View , Liberate Characterization Portfolio , Rapid Adoption Kits , ECSM , RAKs , CCS , Model Files

Breakfast Bytes

2nd WOSET Workshop on Open-Source EDA

During ICCAD earlier in the month, there was the 2nd WOSET, which stands for Workshop…

• 4 min read
open source eda , openroad , woset

System, PCB, & Package Design 

IC Packagers: A Cross-Section of Changes

While 17.4 has only been amongst you for a month, now, I’ve had a few questions regarding…

• 3 min read
APD

System, PCB, & Package Design 

BoardSurfers: Power of Information – Quickly Getting Started with Allegro and OrCAD…

The Allegro and OrCAD 7.4 release is now available for download and installation…

• 1 min read
COS , System Capture , IC Packaging , Cadence Online Support , PSPICE , PCB Editor , Design Entry HDL , EDM , 17.4-2019

Breakfast Bytes

Verifying Processor Security, Part 2

This is the second post about Eli Singerman's keynote at the recent Jasper User Group…

• 5 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

Analog/Custom Design

Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is It Even Possible? (Part 2…

Alright… I’m back again to amuse you with another part on how to set up Package PDK…

• 4 min read
SiP , ICADVM18.1 , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Package Design in Virtuoso , Layout , Virtuoso , System Design Environment , RF design , Modeling , Custom IC Design , Virtuoso Layout Suite , Custom IC , Allegro

Breakfast Bytes

Formally Verifying Processor Security

Intel has had a couple of major events that totally changed their attitude to verification…

• 4 min read
Intel , Jasper User Group , formal , Jasper , JasperGold

PCB、IC封装：设计与仿真分析

RF设计直播课程：如何提高RF前端模块封装设计的迭代效率

大家好，我是Principal Customer Engagement Engineer江亮，从事射频前端模块设计七年，先后受聘于Qorvo，RDA等多家射频半导体研发企业…

• less than a min read
PCB , RF , Chinese blog , PCB设计 , 封装设计 , 直播网课 , 射频前端 , Sigrity , Allegro , 专家培训

Academic Network

CADathlon at ICCAD 2019

Last week, I visited the Cadathlon@ICCAD event at the 2019 International Conference…

• 2 min read

System, PCB, & Package Design 

BoardSurfers: What's Happening Around 17.4-2019?

Allegro and OrCAD 17.4-2019 was released on October 18 and we have since then been…

• 2 min read
17.4 , PCB Editor , SKILL

Breakfast Bytes

OpenROAD: Open-Source EDA from RTL to GDSII

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow,…

• 6 min read
ucsd , dod , openroad , andrew kahng , darpa

Academic Network

Successful Speaker Event—Engaging with Professor in Shanghai

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration…

• 2 min read
university , Cadence Academic Network , academia , university program

Breakfast Bytes

What Does P≠NP Mean?

Recently I wrote about computational software and said that EDA algorithms are all…

• 6 min read
NP-complete , computational software , np-hard

Analog/Custom Design

Virtuosity: Usability Enhancements in the Property Editor

Goes without saying that the Property Editor is the most frequently used feature…

• 2 min read
ICADVM18.1 , Virtuoso Layout Suite L , Property Editor , Custom IC Design , Virtuoso Layout Suite , IC6.1.8
CDNS - Fix Layout Hompage