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Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP(Verification IP:VIP)を発表しました。今回発表されたVIPは…

Cadence Japan
Cadence Japan 4 Dec 2025 • less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
Cadence Japan 1 Dec 2025 • 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Verification

Don’t Let Bugs Slip Through Your RTL Design!

To validate your RTL design, are you still relying solely on simulation? Is there…

Ankita Soni 16 Dec 2025 • 2 min read
FPV , Formal Analysis , formal , SoC , Jasper Apps , SVA , assertions , simulation , Formal verification

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured , CES , USB , interface IP , eUSB2 , AI PC

System, PCB, & Package Design 

Integrity 3D-IC Course Updated for Version 25.1

Unlocking Advanced 3D-IC Design: The Updated Integrity 3D-IC Course The semiconductor…

Vince Kim 15 Dec 2025 • 1 min read
3D-IC , package design , Integrity System Planner , Signal Integrity , interposer

Digital Design

Test Smarter, Not Harder: Explore Cadence’s Hands-On DFT Training Journey

In today's competitive semiconductor industry, robust testing methodologies are essential…

KShubham 15 Dec 2025 • 7 min read
DFT , Modus DFT , Genus Synthesis Solution , ATPG

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Two New Courses to Refine Your PI Skills

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

Vince Kim 15 Dec 2025 • 3 min read
Topology Workbench , Power Integrity , OptimizePI , Signal Integrity , Thermal Analysis , Celsius PowerDC

Verification

Virtualization, Collaboration, and Software at SDV Europe

The SDV Europe conference took place in Berlin (Germany) last week. It was a meeting…

JEngblom 15 Dec 2025 • 6 min read
Automotive , virtual platforms , software-defined vehi , software development

System, PCB, & Package Design 

System Analysis Knowledge Bytes: NEW COURSE - PDN and Voltage Ripple Analysis

The System Analysis Knowledge Bytes blog series explores the capabilities and potential…

Vince Kim 15 Dec 2025 • 3 min read
Sigrity and Systems Analysis , Sigrity X , Topology Workbench , Power Integrity , OptimizePI , Signal Integrity , PDN Analysis

Verification

What's New in PSS 3.0? Key Additions to the Portable Stimulus Standard

The Portable Stimulus Standard (PSS) Language Reference Manual (LRM) has evolved…

OK202502201742 14 Dec 2025 • 6 min read
SoC verification , Perspec , SoC , pss

Analog/Custom Design

Virtuoso Studio: Navigating Smarter - Introducing the Virtuoso Dashboard

The Virtuoso Dashboard brings a unified, streamlined way to manage every window and…

Vipin Singh 12 Dec 2025 • 4 min read
Virtuoso Studio , Custom IC Design

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured , CES , USB , interface IP , eUSB2 , AI PC

Analog/Custom Design

Virtuoso Studio: Stay Notified, Stay Productive-Introducing Notification Display

The latest update to Virtuoso Studio introduces a smarter, more seamless way to stay…

Vipin Singh 11 Dec 2025 • 3 min read
Virtuoso Studio , Custom IC Design

Analog/Custom Design

Demystifying Standard Cell Characterization with Cadence Liberate

In the constantly evolving field of semiconductor design, accuracy and performance…

Rajshekharayya 10 Dec 2025 • 3 min read
Standard cell design , Standard Cell , nldm , characterization , library characterization , Custom IC Design , ECSM

System, PCB, & Package Design 

Revolutionizing Design: Cadence Community Forums Empowering AI-Driven Innovation

As AI-driven design gains momentum, Cadence is leading the way, leveraging agentic…

Renu Vibha 9 Dec 2025 • 1 min read
MSA , TECHNICAL FORUMS , PCB design , Allegro PCB Editor

Corporate News

Thermal Management in 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies

As three-dimensional integrated circuit ( 3D-IC ) technology becomes the architectural…

Reela Samuel 9 Dec 2025 • 7 min read
Celsius Thermal Solver , Allegro X AI , Voltus IC Power Integrity , Integrity 3D-IC Platform , advanced packaging , 3D-IC Technology

Computational Fluid Dynamics

Significance of the High Lift Prediction Workshop for the CFD Community

The HLPW initiative continues to shape the path forward for more reliable, consistent…

Veena Parthan 8 Dec 2025 • 3 min read
CFD , Aerospace , Meshing , Fidelity Pointwise , high-lift prediction

System, PCB, & Package Design 

IC Packagers: Optimizing Connectivity Between Die Escape Routing and BGA Balls

Package designers need to add escape routes to a die to facilitate further package…

JFLepere 8 Dec 2025 • 4 min read
breakout routing , connection optimization , Allegro X Advanced Package Designer , escape routing , ISP , IC Packagers , Integrity System Planner , PCB design , allegro x , Allegro

Verification

Smarter Chips, Faster Checks: GravityXR Leading the XR Verification Shift

As XR technology accelerates, complexity rises—but speed to market remains the ultimate…

HSV Marketing 5 Dec 2025 • 2 min read
performance , AVIP , GravityXR , virtual platforms , cadence , debug , Palladium , hybrid , Emulation , XR , testbench , verification

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP(Verification IP:VIP)を発表しました。今回発表されたVIPは…

Cadence Japan 4 Dec 2025 • less than a min read
news story , Verification IP , featured

Digital Design

Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility

The world's insatiable demand for compute will only continue to increase with the…

Rod M 4 Dec 2025 • 5 min read
Genus , Tempus , pegasus , Jasper , neoverse , Innovus , certus , Quantus , ARM , cloud computing
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