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Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Sunday Brunch Video for 12th May 2019

https://youtu.be/E61e34IbaRE Made at CDNLuve EMEA (camera Andrea Huse) Monday: Statistical…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

通过人工神经网络探讨信号完整性的未来

想象一下，如果电脑或机器人可以完成所有枯燥乏味的工作，我们就能享受生活、做更多有意义的事。这些绝对是许多学术界、工业界研究人员的愿望。工程师的最终梦想是，按下一个…

• 1 min read
SI , Chinese blog , 人工神经网络 , 中文 , Sigrity , SystemSI , 信号完整性

Digital Design

HLS Optimizations You Can't Do By Hand

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable…

• 3 min read
High-Level Synthesis , Stratus , SystemC , HLS

Breakfast Bytes

150th Anniversary of the Transcontinental Railroad

150 years ago, technology meant railroads, not semiconductors. I mean, precisely…

• 4 min read
railroad

System, PCB, & Package Design 

Finally, A Certified and Correlated Reference Flow for Advanced Package Designs

As transistor device scaling gets closer and closer to physical limits, more and…

• 2 min read
advance packaging , Silicon-interposer 2.5D package-based test , reference flow , Samsung , CDNLive 2019 , package design , DesignCon 2019 , FO-PLP , Sigrity , CDNLive San Jose , Package signoff , Advanced Package design and sign-off reference flow

Analog/Custom Design

Virtuosity: The Top 3 Post-Layout Enhancements in Analog Design Environment

Have you ever wanted to sweep DSPF files across corners, plot terminal current and…

• 4 min read
ADE Explorer , post-layout , DSPF , Virtuoso Analog Design Environment , postlayout , Virtuosity , ADE Assembler

Breakfast Bytes

Intel at Linley

At the recent Linley Spring Microprocessor Conference, there were two presentations…

• 4 min read
Intel , Linley

Verification

Concurrent Actions in Specman: Part 2

In the previous blog: Concurrent Actions in Specman , we discussed the existing options…

• 4 min read
Specman , Specman/e , Specman e , concurrency , specman elite

Breakfast Bytes

How Do Out-of-Order Processors Work Anyway?

I've been meaning to write a post on how out-of-order processors work, but one challenge…

• 8 min read
processor , Linley , red hat , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays - Limitations of Scan Compression QoR

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital…

• less than a min read
Whiteboard Wednesdays , modus , Scan Compression

The India Circuit

A Special Day for Cadence India

A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate…

• 1 min read
One Cadence-One Team , Volunteer Time Off , Cadence India , Rise Against Hunger

Breakfast Bytes

JasperGold: the Next Generation

Formal verification has gone through a number of eras. In the early 1990s, it was…

• 3 min read
formal , machine learning , JasperGold , Formal verification , verification

Analog/Custom Design

Virtuoso Video Diary: What's New in Reliability Setup

Read this blog to know about the enhancements made to the reliability options form…

• 3 min read
Stress Analysis , Analog Design Environment , relxpert , ICADVM18.1 , ADE Explorer , MMSIM , ADE XL , ADE , ISR3 , reliability options , Virtuoso Analog Design Environment , Spectre , ADE-XL , Virtuosity , Virtuoso Video Diary , aging , reliability analysis , Custom IC Design , IC6.1.8 , reliability , ADE Assembler

Breakfast Bytes

Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red

I wrote last Friday in my post TSMC: Zero Excursion, Zero Defect about the statistical…

• 6 min read
statistical power

Digital Design

A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss …

• 1 min read
effective resistance , electromigration , clamps , electrostatic discharge , current density , differential voltage , EPS , Voltus , rule file , parallel processing , Innovus , EM , Charged Device Model , massively parallel , bump , ESD

Breakfast Bytes

Sunday Brunch Video for 5th May 2019

https://youtu.be/ICpG3ouDIyQ Made at Nathan's Tesla (camera Sean) Monday: Andy Bechtolsheim…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: Make Menus Your Own – Customizing Menus and Toolbars with Things You…

Flexibility and the ability to customize the software/environment to your own personal…

• 7 min read
Allegro PCB Editor , SiP Layout , SKILL

PCB、IC封装：设计与仿真分析

电路/硬件设计工程师如何选择原理图设计工具

当谈到在EDA领域选择原理图设计工具时，没有人可以找到万能的解决方案。多变的因素加之不尽相同的个人偏好，使得“最好的原理图设计工具是什么？”这个问题始终没有一个统一的答案…

• less than a min read
Allegro System Design Authoring , Chinese blog , 原理图设计 , 原理图 , 硬件设计 , 中文 , 电路设计 , Allegro

Breakfast Bytes

TSMC: Zero Excursion, Zero Defect

At the recent TSMC Technology Symposium, JK Wang, the SVP of fab operations, talked…

• 3 min read
TSMC , TSMC Technology Symposium
CDNS - Fix Layout Hompage