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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix 007 Is Now Available

The HotFix 007 (QIR 1, indicated as 2020 in the application splash screens) update…

• 4 min read
OrCAD Capture , EDM , Allegro Package Designer , ECAD-MCAD Library Creator , Allegro System Capture , Allegro PCB Editor

Digital Design

Library Characterization Tidbits: Understanding the Liberate AMS Command-Line Fl…

Read to know about the Liberate AMS command-line flow.

• 3 min read
Liberate AMS , Digital Implementation , command line flow , mixed-signal characterization , RAKs

Breakfast Bytes

Sophie Wilson: The 2020 Wheeler Lecture (Multicore to Today)

This is the second post continuing from yesterday's post Sophie Wilson: The 2020…

• 7 min read
processor , moore's law , amdahl's law , ARM , microprocessor , ARM1

Learning and Support

Come Join Us for a SystemVerilog Real Number Modeling Seminar!

Looking to improve your SystemVerilog? On June 17th, 2020, there’s a webinar going…

• less than a min read
SystemVerilog , real number modeling , webinar , seminar

System, PCB, & Package Design 

IC Packagers: Welcome to the Dark Side

The 7th ISR (HotFix 007 or QIR1) for the 17.4 release is available for download now…

• 4 min read
Allegro Package Designer , Allegro PCB Editor

Analog/Custom Design

Virtuosity: Voltus-Fi-XL FAQ — Your Questions, Our Answers

Do you want to know the hows and whys of Voltus-Fi? Then don’t miss to get a copy…

• 2 min read
ICADVM18.1 , Voltus-Fi-XL , PGV , Electromagnetic analysis , IR drop , Custom IC Design , IC6.1.8 , EMIR

Breakfast Bytes

Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore)

Since I was an undergraduate studying computer science at what was then called the…

• 7 min read
wheeler , Cambridge , moore's law , amdahl's law , sophie wilson , ARM , ARM1

Breakfast Bytes

Take a Cadence Masterclass and Get a Badge

Many of us are locked down, working from home, or at the very least not going to…

• 4 min read
digital badge , blended training , training

Analog/Custom Design

Virtuoso Meets Maxwell: Finite Element Can Add Clarity

This blog helps you explore the features that make Clarity an obvious choice when…

• 10 min read
ICADVM18.1 , VLS EXL , FEM , VRF , EM Solver , Virtuoso RF Solution , Electromagnetic analysis , Clarity 3D Solver , Finite Element Method , Custom IC Design

Analog/Custom Design

Virtuosity: The Latest Virtuoso ADE Usability Enhancements

Since IC6.1.8/ICADVM18.1 was released we have continued our drive to improve the…

• 9 min read
Analog Design Environment , ADE Explorer , Rapid Adoption Kit , ViVA , usability , Custom IC Design , ADE Assembler

カスタムIC／ミックスシグナル

Virtuosity: 先端ノード用デバイスレベル配線-Trunk-to-Trunk Mesh配線

トランク（幹線）生成の次のステップは、トランクの相互接続（幹線間接続）です。Virtuoso®デバイスレベル配線のブログシリーズのこのブログでは、新しいTrunk…

• less than a min read
Trunk generation , Interactive Routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , trunk creation , Virtuoso , Generate Trunk , Virtuosity , mixed signal , japanese blog , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite

カスタムIC／ミックスシグナル

Virtuosity: デバイスの配置とルーティングの自動化-グリッド生成

Virtuoso®自動デバイスレベル配置およびルーティングシリーズの次の投稿です。 最初の投稿では、自動化されたデバイスレベルの配置およびルーティングソリューションの必要性について話しました…

• less than a min read
ICADVM18.1 , Automated Device-Level Placement and Routing , VPR , Automatic Placement , Advanced Node , Virtuoso , Virtuosity , japanese blog

PCB設計／ICパッケージ設計

BoardSurfers: 正しさのその先へ – デザイン／配線の改善と最適化

PCBレイアウトエディタは、設計が正しいことを確認するために、コンストレイント(制約条件)とルールという形式を通じて、多くのチェックを提供します。DFMルールを利用することで…

• less than a min read
PCB , APD , japanese blog , japan blog

Breakfast Bytes

ETS2020: Functional Safety

One of the keynotes for the European Test Symposium 2020 (ETS2020) was by Cadence…

• 6 min read
Automotive , functional safety , ets2020 , Test , european test conference , fusa

Breakfast Bytes

Sunday Brunch Video for 7th June 2020

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: The Five Waves…

• less than a min read
sunday brunch

RF Engineering

Solving RFIC and RF Module Design Issues

When creating new RFIC modules, designers typically need an array of tools and applications…

• less than a min read
RF , Virtuoso RF Designer , ICADVM18.1 , RFIC , Virtuoso Meets Maxwell , Virtuoso RF , RF design , Custom IC Design , Custom IC

カスタムIC／ミックスシグナル

Virtuosity: 先端ノード用デバイスレベル配線 ‐ Generate Trunksの使用

このVirtuoso®デバイスレベル配線のブログシリーズの2回目以降では、トランク（幹線）とツイッグ（枝配線）がどのようにツリー構造を構築するかについて説明します…

• less than a min read
Trunk generation , Interactive Routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , Layout EXL , Layout Suite , trunk creation , Virtuoso , Generate Trunk , Virtuosity , japanese blog , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

Modeling with Water

A couple of years ago I wrote a post using the famous quote by statistician George…

• 6 min read
Models , bay model

Analog/Custom Design

Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional Verification…

What if there existed a seamless way to pass verified design blocks freely between…

• 2 min read
AMS , mixed signal design , AMS Designer , mixed signal solution , Verilog-AMS , analog , analog/mixed-signal , Virtuoso , RNM , wreal , AMS Verification , mixed-signal verification , verification
CDNS - Fix Layout Hompage