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Computational Fluid Dynamics: This Week in CFD

John Chawner

It's a short week here at Cadence CFD as we celebrate the Juneteenth holiday today. But CFD doesn't take time off as evidenced by the latest round-up of CFD news. There are several really cool CFD applications profiled this week including a m...
- 18 Jun 2021
PCB、IC封装：设计与仿真分析: Cadence 收购计算流体动力学公司 NUMECA

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Cadence to Acquire Computational Fluid Dynamics Company NUMECA"。 space 今年年初，Cadence 收购了NUMECA International公司，扩大了公司在计算流体动力学 (CFD) 方面的系统分析能力。NUMECA 是 CFD、网格生成、多物理场仿真和优化领域的...
- 17 Jun 2021
Analog/Custom Design: Virtuosity: Bindkeys in Virtuoso Layout Suite

Sucharita

You can use Virtuoso keyboard shortcuts called bindkeys in Virtuoso Layout Suite to perform certain tasks. Check out this blog to see how you can download a printable document for bindkeys used in different Virtuoso Layout applications.
- 17 Jun 2021
Breakfast Bytes: The EVS Codec: The Movie

Paul McLellan

I have written before about standards in general (including one that is 2000 years old) in my post Why Do Layout Designers Say "Stream Out"? and the new cell-phone vocoder standard in Cadence and Standards...and A New Codec for Yo...
- 17 Jun 2021
System, PCB, & Package Design : (P)SpiceITUp: The Power of Options in Managing Accuracy and Speed Using Relative and Absolute Tolerances

mrigashira

The tolerances are not unique to only PSpice or simulators, they are part of any problem requiring numerical methods of solutions involving reiterative steps that finally converge. For example, many data analysis applications will require ABSTOL and RELTOL. Let us then first try to understand what these tolerances exactly...
- 17 Jun 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: Spectreアナログフォルト解析の紹介

Custom IC Japan

プロセスの微細化に伴い、不具合が発生しやすくなったため、チップテストの要求が厳しくなっています。これらの欠陥はフォルトとしてモデル化され、回路シミュレータに提供されてフォルト解析が行われます。Legato Reliability Solutionの一部であるSpectre® Fault Analysisは、トランジスタレベルのシミュレーション機能を提供しており、アナログのテスト手法で有効にすることで、重要なテストパターンを特定し、テストカバレッジを向上させることができます。以下のフロー...
- 16 Jun 2021
Spotlight Taiwan: Allegro X 設計平台 - 下一代智慧系統設計的新革命

candyyu

原文出處: Allegro X, the Design Platform for the Next Generation of Intelligent System Design作者: Paul McLellan開發Cadence產品工具組合的一大宗旨之一，是能無縫整合共用資料庫的相關工具、如此檔案就無須經轉譯。舉例來說，利用Google翻譯做個有趣的實驗，文字從法文轉換成英文之前，若先從法文翻成日文，再從日文翻成英文，似乎總會喪失某些語意的清晰度。過去我們習慣把PCB設計當作「設計印...
- 15 Jun 2021
Digital Design: Voltus Voice: Unleashing the Power of Intelligent System Design Strategy - A chat with Rajat Chaudhry

Priya E Joseph

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how Voltus has introduced several innovative technologies to address power signoff challenges, while integrating seamlessly with Cadence IC, package, PCB, and system tools.
- 15 Jun 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: EMX Planar 3Dでのポート定義

Custom IC Japan

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC-パッケージ設計環境...
- 15 Jun 2021
Breakfast Bytes: Dr C.C. Wei's Keynote at TSMC Symposium

Paul McLellan

At the recent TSMC 2021 Online Technology Symposium, the keynote to open the show was delivered by Dr C. C. Wei, TSMC's CEO. In addition to C.C. himself, there were guest appearances by Lisa Su, CEO of AMD, by Cristiano Amon, CEO-in-waiting of Q...
- 15 Jun 2021
Digital Design: Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want to Resolve It?

Neha Joshi

Design for Test (DFT) techniques provide measures to test the manufactured device for quality and coverage comprehensively. You might encounter Error or Warning messages while inserting scan during the synthesis stage.

We know it is a little tricky to resolve DFT Errors and Warning. But don't worry!! We can help provide guidance. For example, the Error or Warning could be related to checking DFT rules, reporting, defining…
- 14 Jun 2021
Breakfast Bytes: RSAC: The Cryptographers' Panel

Paul McLellan

The Cryptographers' Panel was moderated by RSA's Zulfikar Ramzan, and featured Ron Rivest (the R of RSA), Adi Shamir (the S of RSA), Ross Anderson (professor of security engineering at Cambridge University and Edinburgh University—as it...
- 14 Jun 2021
Verification: Training Insights — Metastability-Aware Verification: Elevate Your Signoff with JasperGold CDC App!

Nizar Hanna

I hope you enjoyed and got good insights about the Cadence® JasperGold® CDC during the previous CDC webinar "Still Relying on Static-Only CDC Signoff? Introducing the JasperGold CDC App". If you didn't have the chance to attend it, we are recommending you to visit the Training Byte webinar recording here before joining this webinar.

Clock domain crossing (CDC) issues remain a major problem for designers…
- 13 Jun 2021
Breakfast Bytes: Sunday Brunch Video for 13th June 2021

Paul McLellan

https://youtu.be/T9V_61_3ZVA Made in San Francisco Botanical Garden (camera Carey Guo) Monday: Hardware Hacking Party Tricks Tuesday: TSMC's 3DFabric Wednesday: Allegro X, the Design Platform for the Next Generation of Intelligent System Des...
- 13 Jun 2021
Breakfast Bytes: What Is a System? It's Turtles All the Way Down...or Fleas

Paul McLellan

According to Steven Hawking, in his book A Brief History of Time, Bertrand Russell once gave a public lecture on astronomy. He described how the earth orbits around the sun and how the sun, in turn, orbits around the center of a vast collection of st...
- 11 Jun 2021
Computational Fluid Dynamics: Not-to-miss Live Webinars about CFD This Month

AnneMarie CFD

In June once more we launch a series of not-to-miss live webinars on various CFD topics. It's a great opportunity to learn about the latest advancements in CFD simulation, see our tools in action first-hand and ask any questions you may have str...
- 10 Jun 2021
Breakfast Bytes: RSAC: Hacking a Solar Power Controller—And Pretending to Generate a Gigawatt

Paul McLellan

At the recent RSAC, there was a great presentation by Waylon Grange on hacking the embedded software in his neighbor's solar power controller. He was stuck at home during lockdown, and his neighbor had solar panels installed. He emphasized that t...
- 10 Jun 2021
カスタムIC／ミックスシグナル: Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout Product Pageのご案内

Custom IC Japan

誰もが迅速な解決策を探す目まぐるしく動く世界に対応するには、関連する全ての情報を入手できるワンストップの学習リソースがとても役立ちます。Cadence Learning and Support ポータルに用意されている様々なページやセクションを、当社の製品やテクノロジーに関する情報に素早くアクセスするために是非ご活用下さい。このシリーズの前回のブログではCadence Learning and Supportポータルに最近追加されたCustom IC Design Flow / Methodo...
- 10 Jun 2021
RF /マイクロ波設計: μWaveRiders:コネクテッドカーを駆動する RF/マイクロ波技術

RF Design Japan

The Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るために、Subscribe...
- 9 Jun 2021
RF Engineering: μWaveRiders: RF/Microwave Technology Driving the Connected Car

TeamAWR

A recently published white paper, RF/Microwave Technology Driving the Connected Car, discusses how wireless communications and mmWave radar systems enable next-generation vehicles with a host of functions, ranging from safety and navigation features to infotainment and remote entry/control. Along with the deployment of 5G ultra-reliable low latency networks and their potential to support autonomous driving, automotive…
- 9 Jun 2021
System, PCB, & Package Design : ASCENT: Some Basic Rules for Design Verification

Auromala

In part 1 of this blog post, we covered the model-less aspect of Allegro® System Capture’s Design Integrity solution and now here we are with part 2. So, maybe scrolling through or navigating 200-300 pages of a design to catch logic design ...
- 9 Jun 2021
Breakfast Bytes: Allegro X, the Design Platform for the Next Generation of Intelligent System Design

Paul McLellan

allegro x system design and pcb design with machine learning and unparalleled productivity
- 9 Jun 2021
PCB設計／ICパッケージ設計: ASCENT: Unified Searchを使って最適な部品を見つける

SPB Japan

デザインに適した部品を見つけることは、設計作業の中で最も時間がかかるパートだと言う人もいます。もしそうであるならば、必要なものをすばやく見つけるのに有効な、あらゆる援助を利用することが求められます。必要な部品は、特定のタイプの部品、特定の特性値、特定のメーカー、特定のサイズ、…そのリストに限りはありません。前回のブログでは、Allegro® System Capture がサポートするさまざまなコンポーネントソースについて説明しました。今回のブログでは、コンポーネントソー...
- 8 Jun 2021
Digital Design: A Proven Way to Simulate High-Frequency Electro-Magnetic Effects Using Quantus Extraction Solution

Hitendra

Cadence offers multiple electromagnetic (EM) extraction technologies to model the parasitic effects of interconnect and passive component geometries (see Virtuoso Meets Maxwell: Layered Electromagnetic Modeling For Sufficient Accuracy for detail...
- 8 Jun 2021
Breakfast Bytes: TSMC's 3DFabric

Paul McLellan

I already wrote about TSMC's advanced-node roadmap in my post TSMC: Advanced Technology for Smartphone and HPC Platforms where Yujun Li presented the details of N7, N6, N5, N4, and N3, and other HPC-focused technology. In a sense, she was g...
- 8 Jun 2021

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