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Analog/Custom Design: Demystifying Standard Cell Characterization with Cadence Liberate

Rajshekharayya

In the constantly evolving field of semiconductor design, accuracy and performance are essential. A key step in creating high-quality chip designs is the characterization process, which determines how circuits perform under different specified conditions, including Process, Voltage, and Temperature (PVT) variations. This is where the Characterization tool Cadence Liberate acts as a transformative solution.
Why Standard…
- 10 Dec 2025
System, PCB, & Package Design : Revolutionizing Design: Cadence Community Forums Empowering AI-Driven Innovation

Renu Vibha

As AI-driven design gains momentum, Cadence is leading the way, leveraging agentic AI to transform how engineers innovate, solve complex challenges, and build next-generation systems. Community forums have evolved far beyond simple Q&A space...
- 9 Dec 2025
Corporate News: Thermal Management in 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies

Reela Samuel

As three-dimensional integrated circuit (3D-IC) technology becomes the architectural backbone of AI, high-performance computing (HPC), and advanced edge systems, thermal management has shifted from a downstream constraint to a fundamental design driv...
- 9 Dec 2025
Computational Fluid Dynamics: Significance of the High Lift Prediction Workshop for the CFD Community

Veena Parthan

The HLPW initiative continues to shape the path forward for more reliable, consistent, and robust CFD methodologies, benefiting the entire aerospace industry.
- 8 Dec 2025
System, PCB, & Package Design : IC Packagers: Optimizing Connectivity Between Die Escape Routing and BGA Balls

JFLepere

Package designers need to add escape routes to a die to facilitate further package routing: these routes provide essential pathways for signals to exit the die and reach other parts of the package or PCB. Without well-planned escape routing, signal t...
- 8 Dec 2025
Verification: Smarter Chips, Faster Checks: GravityXR Leading the XR Verification Shift

HSV Marketing

As XR technology accelerates, complexity rises—but speed to market remains the ultimate differentiator. GravityXR is setting the standard with the Cadence Palladium Emulation Platform, delivering MHz-level emulation, automated debugging, and comprehensive system-level coverage. This breakthrough approach empowers teams to catch issues early, streamline workflows, and deliver high-quality XR chips with confidence. Discover…
- 5 Dec 2025
Cadence Japan: ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

Cadence Japan

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは、Ultra Accelerator Link（UALink）、Ultra Ethernet（UEC）、LPDDR6、UCIe 3.0、AMBA CHI-H、Embedded USB v2（eUSB2）、UniPro 3.0などのインターフェースに対応しています。このVIPを活用することで、最新の業界基準に準拠した高品質な...
- 4 Dec 2025
Digital Design: Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility

Rod M

The world's insatiable demand for compute will only continue to increase with the proliferation of AI. As compute demands grow, on-premises chip design becomes more complicated and costly, challenging existing infrastructure due to increased sys...
- 4 Dec 2025
Corporate News: 3D-IC Packaging: Wafer Stacking, Hybrid Bonding, and Interposer/RDL Techniques

Reela Samuel

The semiconductor industry is entering a new era where transistor scaling alone can no longer fuel performance gain. With AI accelerators pushing beyond 2–5TB/s of die-to-die bandwidth, hyperscale systems demanding higher compute density, and m...
- 4 Dec 2025
Digital Design: RTL-to-GDSII Backend Webinar: Couldn’t Make It? We Saved You a Front Row Seat

P Saisrinivas

After finishing my webinar on synthesis to timing signoff flow, including the AI features discussed during the session, I received the following questions:

"I missed the webinar. Do you have the recording?"

“I work on implementation. I missed joining and learn about AI features in Innovus. Can I access the webinar later?"

“I have a glitch due to my Wi-Fi connection. Can you share the recording,…
- 4 Dec 2025
System, PCB, & Package Design : How to Use AI to Optimize Your Power Delivery Network

MSATeam

Modern power delivery network (PDN) design poses numerous challenges. Traditionally, designers rely on target impedance analysis—a widely used and effective starting point for ensuring power integrity (PI). While its simplicity and historical success make it appealing, in today's high-speed, high-density systems, its limitations are becoming more apparent with faster transistor switching and increased current demands…
- 3 Dec 2025
Verification: VESA Adaptive-Sync V2 Operation in DisplayPort VIP

Vaibhav Sirvi

Need for Synchronization
In a computer system, both the GPU as well as the monitor have a certain rate at which they render or update an image, respectively. The rate is nothing but the frequency at which the image is refreshed (updated in the image it shows/displays), usually expressed in hertz, and can vary based on the content displayed on the screen.

Figure 1: Refresh rate requirements under different application…
- 3 Dec 2025
Computational Fluid Dynamics: Professionals in CFD with Judy Susan Jose

Veena Parthan

In this edition of Professionals in CFD, we have Judy Susan Jose, a lead configuration management engineer for the CFD team.
- 2 Dec 2025
System, PCB, & Package Design : Determining Effects on PDN Target Impedance Using Sigrity X

MSATeam

Ensuring a functional power distribution network (PDN) for chips, packages, and PCBs is a challenge for system design engineers facing increasingly difficult design targets and varying design and hardware delivery dates. A CadenceLIVE 2025 presentation is now available on demand that examines work done as part of Project Kuiper, Amazon's low Earth orbit satellite broadband network with a mission to deliver fast, reliable…
- 2 Dec 2025
System, PCB, & Package Design : Empowering Innovation in Abu Dhabi - CadenceCONNECT Middle East

Stephen Smith

Cadence recently had the honor of hosting CadenceCONNECT: Middle East Tech Days at the prestigious Khalifa University in Abu Dhabi. This event was a testament to our commitment to fostering innovation and collaboration in one of the world's most ...
- 2 Dec 2025
Corporate News: Through-Silicon Vias (TSVs): Interconnect Basics, Design Rules, and Performance

Reela Samuel

Through-silicon vias (TSVs) are one of the foundational enablers of modern three-dimensional integrated circuit (3D-IC) technology, providing vertical interconnects that cut through the silicon to connect stacked dies with short, low-latency signal p...
- 2 Dec 2025
Cadence Japan: ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

Cadence Japan

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。
- 1 Dec 2025
Analog/Custom Design: Green, Red, and Blue Lights in the Layout Design — What Do They Indicate?

VEENA G P

As you know, even after generating the layout from the source, there can still be connectivity (binding) mismatches between the schematic and layout. Traditionally, fixing or debugging these issues requires manual navigation through multiple menus to...
- 26 Nov 2025
Verification: ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard

Shyam Sharma

Non-volatile memories like Nand Flash are key components of most modern system-on-chip (SoC). The I/O speeds and bandwidth of these types of memories are seeing tremendous improvements and advances in the underlying technology are making them increasingly used for a large variety of applications. These applications rely on not just the high density that traditionally has been the main benefit of flash memories, but throughput…
- 25 Nov 2025
Life at Cadence: Building Bridges Through Education and Innovation

Yesenia Carrillo

This fall, a group of 11 Cadence employees from Brazil, Germany, India, Italy, the UK, and the US volunteered with Team4Tech and Bindi International on a three-month philanthropic project to develop solutions for educators and communities that levera...
- 25 Nov 2025
Cloud: A New Era of Cadence Managed Cloud Service

Iris Zheng

The Future of Secure, Scalable EDA in the Cloud As the semiconductor industry accelerates toward digital transformation, the need for secure, scalable, and flexible EDA in the cloud has never been greater. Cadence’s Managed Cloud Ser...
- 25 Nov 2025
Corporate News: 2.5D vs 3D-IC: Architecture Tradeoffs, and a Practical Selection

Reela Samuel

As traditional scaling slows and multi-die integration becomes the new engine of semiconductor performance, the question facing every system architect is no longer whether to adopt advanced packaging, but which architecture to choose. The decision be...
- 25 Nov 2025
Computational Fluid Dynamics: Reduce Noise and Improve Fan Performance with Serrated Edges

Veena Parthan

Understanding Noise Reduction in Industrial Fans Industrial fans are widely utilized across various sectors, including manufacturing, automotive, and energy production, playing a vital role in ventilation and cooling. However, a notable drawback of t...
- 24 Nov 2025
Corporate News: Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Corporate

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for AI-based designs, including Ultra Accelerator Link (UALink), Ultra Ethernet (UEC), LPDDR6, UCIe 3.0, AMBA CHI-H, Embedded USB v2 (eUSB2), and UniPro 3.0. These new VI...
- 21 Nov 2025
カスタムIC／ミックスシグナル: Virtuoso Studio: 快適な作業環境 - 新しいディスプレイテーマや可読性の向上

Custom IC Japan

これは、Virtuoso Studio IC 25.1のリフレッシュに関する5部構成のブログシリーズの第2弾です。IC設計における日々の作業をより快適で目に優しいものにするため、導入された新しいDark Gray ThemeやTrueType Fonts表示機能について、より深く掘り下げてご紹介します。
- 20 Nov 2025

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