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Non-volatile memories like Nand Flash are key components of most modern system-on-chip (SoC). The I/O speeds and bandwidth of these types of memories are seeing tremendous improvements and advances in the underlying technology are making them increasingly used for a large variety of applications. These applications rely on not just the high density that traditionally has been the main benefit of flash memories, but throughput…

Compute Express Link (CXL) is revolutionizing data center architecture, with power management emerging as a key area of innovation. Among its power-saving mechanisms, the L0p (Low Power) state plays a pivotal role in reducing energy consumption during periods of low link activity. But what exactly does L0p mean for a CXL link, and how can we ensure its reliable implementation through comprehensive verification?

Did you miss the “Introduction to Low-Power Optimization with Genus Synthesis Solution” webinar because your Wi-Fi thought it was a low-power device and took a nap? Or maybe you left halfway through because your dog scheduled a surprise Zoom call with the neighbour’s cat? Or perhaps you just wanted to see if anyone would notice your dramatic exit (spoiler: we noticed, and we’re still talking about it).…

Memory interleaving is a technique that distributes memory addresses across multiple memory devices or channels. Instead of storing data sequentially in one device, the system alternates between devices at a fixed granularity. It could help improve bandwidth, reduce latency, and enhance scalability. In the context of Compute Express Link (CXL), memory interleaving is facilitated by the HDM (Host-Managed Device Memory) Decoder…

As the industry continues to progress in PCIe, enabling faster and reliable data transfer, with each new generation, PCIe doubles its bandwidth — a change that brings both performance and challenges.

When PCIe 6.0 arrived, one critical feature stood out: Forward Error Correction (FEC). Its inclusion wasn’t optional—it was essential.

To understand why Forward Error Correction (FEC) was introduced…

The semiconductor industry is advancing at an unprecedented pace, driven by the need for higher performance, greater integration, and maximum efficiency. With Moore's Law slowing, innovative approaches like chiplet-based architectures have taken center stage, especially for physical AI designs. We are excited to announce a major milestone: the successful silicon bring-up of the Cadence System Chiplet, a core component…