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Are you looking to level up your digital design skills—one byte at a time? Ohoo! I am supposed to ask this question at the end of this blog.

Ever feel like your brain is a sponge that’s just not soaking up enough? Or maybe you have tried to learn something new and ended up feeling like a cat chasing a laser pointer—excited but ultimately confused? Fear not, my friend! Microlearning is here to save the day, and it…

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be leveraged for depth sensing.

So, ToF? It's all about measuring depth. We've got two main types: Direct ToF (dToF) and Indirect ToF (iToF). dToF is like shouting and waiting for the echo—it measures the actual time it takes for light to bounce back.

Then there's iToF, where one figures out distance by comparing the phase…

In today's world of increasingly intelligent devices, efficient and reliable storage is paramount. Embedded MultiMediaCard (eMMC) has emerged as a crucial component that acts as the internal solid-state non-volatile storage for a wide range of devices handling on-device AI processing. Think of it as a compact, high-performing internal drive built directly into your phone, smart camera, or other embedded systems. This…

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus Standard (PSS) to model your system, you will likely need a way to operate on the memory-mapped registers of various programmable devices within your system. This blog will guide you through the following processes:  

• Creating your PSS register model (or translating existing register metadata to PSS using Perspec’s pss_gen utility…

Low-power DDR (LPDDR) SDRAM has been one of the most widely used memories in the semiconductor market today. It’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and server, automotive, Virtual Reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

On April 9 and 10, 2025, Cadence San Jose hosted the JEDEC LPDDR Task Group face-to-face meeting…

Join Cadence Training and presenters from our CIC experts for this free technical Training Webinar.  
 
The porting of a custom IP block to a new silicon process has traditionally been a manual process. However, the introduction of new algorithms in Cadence’s Virtuoso Studio, including AI/ML techniques, provides a step change in productivity for design migration.  
 
This webinar demonstrates three steps for design migration…

In the automotive industry, there is zero tolerance for field failures, as human safety is at stake. Given the rapid evolution of the electric vehicle (EV) and autonomous driving technologies, it is critical to accelerate the development of robust designs to remain competitive.

Simulation of the PCB and IC package components within complex electronic automotive systems plays a pivotal role in ensuring that designs meet…

The world of Electronic Design Automation (EDA) is fascinating, where we transform humble grains of sand into sophisticated silicon chips that power our modern lives. Imagine this journey as a grand adventure, akin to building a bustling city from scratch. Buckle up as we take you through the highlights of our latest course, "Introduction to Electronic Design Automation.

Imagine standing on a beach surrounded by…

The recent HBM4 specification announced by JEDEC is great news for developers of AI training hardware. HBM4 is the latest specification in the rapidly evolving High Bandwidth Memory (HBM) DRAM standard, providing 2TB/s of memory performance and higher density up to 64GB (32Gb 16-high), according to JEDEC. "The advancements introduced by HBM4 are vital for applications that require efficient handling of large datasets…

Cadence's multiphysics system analysis (MSA) portfolio grew in both depth and breadth throughout 2024. Across electromagnetics (EM), signal and power integrity (SI/PI), thermal and electronics cooling, computational fluid dynamics (CFD), and data center digital twinning, we offer in-design analysis (IDA) solutions that streamline workflows by integrating multiphysics analyses directly into design platforms for electronic…

We are witnessing a dramatic rise in disaggregation and a lot of discussion around chiplet-based design. There are multiple reasons for it: as monolithic dies grow larger, they hit reticle limits and much before that the yield drops precipitously making them uneconomical. That is where monolithic designs are headed and to stay economical, they need to disaggregate into chiplets. This is not the only reason. Cost per transistor…

Thermal challenges in 3D-IC designs can cause a significant risk in meeting performance specifications. While the pace of Moore’s Law has slowed in recent years, system technology co-optimization (STCO) promises to mitigate technology scaling bottlenecks with system architecture tuning based on emerging technology offerings, including 3D technology.

AI-driven inference accelerators continue to expand the 2D system…