Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

RF /マイクロ波設計

新しいミリ波MIMOレーダーシステムの設計

レーダーは、反射した電波を使用して、物体の距離、角度、または速度を決定します。かつては航空宇宙および防衛産業の独占的な領域であったこれらの検出システムは、現在、消費者産業…

• 1 min read
AWR Design Environment , AWR AXIEM , RF design , AWR Microwave Office , Radar systems , japanese blog , MIMO , Visual System Simulator(VSS)

RF Engineering

Design of a Novel mmWave MIMO Radar System

Radar uses reflected radio waves to determine the range, angle, or velocity of objects…

• 13 min read
AWR Design Environment , AWR AXIEM , RF design , AWR Microwave Office , Radar systems , mmWave MIMO radar , Visual System Simulator (VSS) , MIMO

Breakfast Bytes

Arm/Cadence on Implementing Advanced Microprocessors in Advanced Processes

Late in January, Cadence and Arm ran a joint webinar on implementing advanced microprocessors…

• 2 min read
graviton , neoverse , digital full flow , ARM

Verification

Taking LPDDR5 to the Next Level

To cater to ever-increasing bandwidth demands from low-power DRAMs especially for…

• 2 min read
Verification IP , Memory , VIP , JEDEC , lpddr5 , lpddr5x

Verification

DisplayPort 128b/132b Concurrent LTTPR Link Training

Before a video frame can be sent, the Source (DP-TX) must complete link training…

• 1 min read
Verification IP , DisplayPort , TripleCheck

Digital Design

Understanding Clock Gating Report and Cells

Hi everyone, Are you interested in reducing the power dissipation of your design…

• 2 min read
digital badge , blended training , Genus , training bytes , Digital Implementation , online training , cadence learning and support

System, PCB, & Package Design 

Sigrity and Systems Analysis 2021.1 Release Now Available

The Sigrity and Systems Analysis 2021.1 release is now available for download at…

• 9 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , SPEEDEM , Clarity 3D Transient Solver , Sigrity Suite , Mesh Refinement , OrCAD/Allegro 17.4 (SPB174) , SystemSI , Clarity 3D Solver , Layout Workbench

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre X RF解析の使用

2020年9月末にSPECTRE 20.1ベース・リリースにてSpectre® X-RFがリリースされました。Spectre X-RFテクノロジはSpectreのRF解析にSpectre…

• less than a min read
+xdp , +preset , Spectre X-RF , japanese blog , spectre x , Spectre X distributed simulation , Spectre X Simulator

RF /マイクロ波設計

Cadence AWR Design EnvironmentのE-ニュースレター(2021年1月)

日本語翻訳版をお届けします。ぜひ最新の製品に関する最新の情報をご確認ください。 このニュースレターの英語版は こちら です。 Cadence AWR Design…

• less than a min read
RF , awr , japanese blog

System, PCB, & Package Design 

BoardSurfers: Training Insights: How to Assess Electrical Performance of Package…

In this blog, you will be taking an IC package design from Allegro® Package Designer…

• 4 min read
APD+ , 17.4 , Cadence Online Support , APD , Allegro Package Designer , 17.4-2019

Analog/Custom Design

Start Your Engines: Automatic Configuration Creation for a Mixed-Signal Test Ben…

In this post, I will cover how you can easily create an automatic configuration for…

• 3 min read
mixed signal design , Automatic Configuration Creation , ADE Explorer , AMS Designer , Start Your Engines , HED , analog/mixed-signal , mixed-signal verification , ADE Assembler

Verification

HyperRam as DRAM for Some Applications!!!

Applications like Automotive, Industrial control panels, Smart Home, Smart watches…

• 1 min read
Verification IP , hyperRAM , Memory , VIP , HyperBus , verification

Verification

Training Insights - Clean RTL Faster Without Simulation! Here’s How.

RTL designers are challenged by increasingly complex designs. They’re also expected…

• 2 min read
Functional Verification , RTL , webinar , JasperGold

Breakfast Bytes

Offtopic: All the Days

It's a weird confluence of days this weekend. It is the Chinese New Year on the 12th…

• 1 min read
offtopic

カスタムIC／ミックスシグナル

Virtuoso Video Diary: Split Symbolsとは

何百ものピンを持つ大きな symbol は管理するのが難しく、デザインを乱雑にします。より複雑なデザインと高度なテクノロジーにおいてブロックを分割することは、どのようなデザインでも便利な機能になっています…

• less than a min read
split symbols , Virtuoso Schematic Editor , custom/analog , splits , Virtuoso , ICADVM20.1 , japanese blog , create split symbols , create splits , Custom IC

Analog/Custom Design

Virtuoso Video Diary: Performance Diagnostic Tool – An MRI Scanner for Virtuoso

You can now use the Performance Diagnostic tool in the Virtuoso custom IC design…

• 3 min read
performance diagnosis , Virtuoso , performance diagnostic , ICADVM20.1 , Custom IC Design , Custom IC , Virtuoso scanner

Academic Network

BarCamp? 2021 DATE BarCamp!

The following text was written by Georg Gläser, one of the organizers of the edaBarCamp…

• 2 min read
DATE , Cadence Academic Network , BarCamp , bcAtDATE , DATEBarCamp

Life at Cadence

An Amazing Season to Give

Giving has always been a special part of our culture at Cadence. It’s one of the…

• 4 min read

Breakfast Bytes

DATE: Making Fabs Smarter

One of the keynotes at the recent DATE 2021 was local. Or would have been local if…

• 7 min read
DATE , ST , smart industry , date 2021 , ST Microelectronics
CDNS - Fix Layout Hompage