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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Computational Fluid Dynamics

Rank-N Nonlinear Harmonic Method Unlocks More Precise And Reliable Turbomachinery…

The NLH Rank-n feature unlocks the possibility of simulating unsteady phenomena across…

• 1 min read
CFD , turbomachinery , webinars , Computational Fluid Dynamics , fluid dynamics , nonlinear harmonic , CFD Applications , simulation software , rank-n , nlh , Turbo , simulation

Breakfast Bytes

Jack Dongarra Receives Turing Award

Last week, the ACM announced that Jack Dongarra was being honored with the 2021 Turing…

• 4 min read
turing award , supercomputer

SoC and IP

TWS Earbud Design: Scaling up

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier…

• 9 min read
Tensilica DSPs , Tensilica

SoC and IP

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

• 5 min read
featured , Tensilica

Verification

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

• 6 min read

Breakfast Bytes

Intelligent System Analog Design

There are many perceptions about analog design that might have been true once. For…

• 6 min read
analog , Virtuoso , mixed signal , Virtuoso Layout Suite EXL

PCB設計／ICパッケージ設計

BoardSurfers: Allegro PCB Editorでの寸法データ入力に関する概要

プリント基板がより複雑かつ軽量になっていく中、費用対効果が高く信頼性の高い基板の設計・製造は、これまで以上に重要となっています。デザインの詳細情報が不正確／不完全では…

• less than a min read
17.4 , BoardSurfers , manufacturing , japanese blog , Allegro PCB Editor , Allegro

Computational Fluid Dynamics

Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

Flow solvers must be able to read the type of meshes behind them, and as most flow…

• 4 min read
CFD , Automated meshing , mesh , structured grids , Computational Fluid Dynamics , fluid dynamics , structured meshing , CFD Applications , unstructured meshing , simulation software , Meshing , simulation , unstructured grids

Breakfast Bytes

The All-Purpose EDA Keynote

Today, it is April 1st and so it is tempting to do some spoof post, but most of those…

• 5 min read
edagraffiti , Blogging , parody , keynote

Life at Cadence

Celebrating Women's History Month with Girl Geek X!

To celebrate Women’s History Month in March, Cadence partnered with Girl Geek X for…

• 1 min read
inclusion , Women at Cadence , women , Women's History Month , girl geek , diversity , Women in Technology

Breakfast Bytes

DVCon: There Be Dragons!

At the recent DVCon, there was a panel session titled SoC Verification Hidden Dragons…

• 12 min read
formal , Emulation , DVcon , simulation , verification

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.028 is Now Available

The HotFix 028 (QIR4, indicated as 2022 in the application splash screens) update…

• 6 min read
Cadence Design Systems , 17.4 , PSpiceA/D , PSPICE , PCB Editor , 17.4-2019 , OrCAD , PCB design , Allegro System Capture , Pulse , Allegro

Analog/Custom Design

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator

DSPF files are an integral part of post-layout simulations. This blog introduces…

• 5 min read
spectre aps , post-layout simulation , EMIR Analysis , EMIR Simulation , DSPF , netlist , Spectre , Spectre X Simulator , EMIR

CFD（数値流体力学)

Illinois Blowerは流体シミュレーションによってファンの性能を44％改善

石油化学およびその他の産業では、空気の換気や500°C以上の有害な塩化物ガスの処理のためにファンを使用しています。これらのファンの最大運転回転速度は業界標準によって管理され…

• less than a min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , japanese blog , simulation

Computational Fluid Dynamics

Shortage of Chips a Challenge for Vehicle Electrification

Electric Vehicle (EV) market growth, along with the bourgeoning investments in autonomous…

• 5 min read
battery capacity , Automotive , gallium nitride , electric vehicles , intelligent manufacturing , chip production , Silicon chips , silicon carbide

Computational Fluid Dynamics

Illinois Blower Increases Fan Performance by 44% with Fluid Dynamics Simulation

Illinois Blower develops and builds custom centrifugal fans and blowers for a variety…

• 5 min read
CFD , turbomachinery , fans , Computational Fluid Dynamics , fluid dynamics , simulation software , simulation

Analog/Custom Design

Virtuoso ICADVM20.1 ISR24 and IC6.1.8 ISR24 Now Available

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso ADE Explorer , Virtuoso Layout Suite , Custom IC , Virtuoso ADE Assembler , IC6.1.8

Breakfast Bytes

ESD Alliance CEO Outlook (and the Kaufman Dinner)

The ESD Alliance has two events coming up in the next couple of months, both of which…

• 2 min read
kaufman dinner , semi , ceo outlook , esd alliance

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: RF回路でのカスタム受動デバイス – デバイスかそれともインターコネクトか

'Virtuoso Meets Maxwell' はVirtuoso RF ソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
S-parameter , Extraction , Smart View , Layout versus schematic , pegusas , RFIC , parasitic , LVS , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic Solver , Electromagnetic analysis , EMX , Quantus Extraction Solution , graybox , ICADVM20.1 , japanese blog , blackbox , Quantus , Custom IC Design , EMX Solver , VMM
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