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Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
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Blog - Post List

Latest blogs

Digital Design

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

• 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Life at Cadence

Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Understand the role that density and compact design optimization play when designing…

• 5 min read
F1 , optimization , density , formula 1

Breakfast Bytes

USB-C – The Least Standard Standard Ever

In a post in our verification blog , Neelabh Singh told us that USB4 Version 2.0…

• 3 min read
usb 4.0 , USB , USB-C

Verification

Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Te…

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol…

• 3 min read
CXL , Verification IP , cadence , Functional Verification , VIP , PCIe , coherency , TripleCheck

Breakfast Bytes

HOT CHIPS: Arm's Morello

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some…

• 5 min read
morello , hot chips , ARM , cheri , capability

System, PCB, & Package Design 

Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Desi…

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering…

• less than a min read
SI , PI , IC , SSN anlysis , IC Packaging , Sigrity XcitePI , Co-Analysis , Power Integrity , CadenceLIVE China , Advanced-IC Package design , silicon interposer , Signal Integrity , 2.5D HBM , cadencelive , Sigrity SystemSI , Clarity 3D Solver , simulation

Verification

CXL 3.0 Scales the Future Data Center

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen…

• 4 min read
CXL , Verification IP , Memory , System Design and Verification , VIP , PCIe , Funcional Verification , coherency , PCIe 6.0 , AI , data centers , cloud computing , verification

Breakfast Bytes

CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Congress and the military love to come up with cute acronyms for programs, and so…

• 3 min read
RF , SiP , ship , ship-rf , 3dhi

Verification

Unraveling New Introduced PCIe 6.0 L0p

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , VIP , PCIe , pcie gen6 , verification

Computational Fluid Dynamics

Streamline Reading and Writing Files from Fidelity Pointwise

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was…

• 6 min read
Meshing Monday , geometry cleanup , Computational Fluid Dynamics , engineering , simulation software , Mesh Generation , Cadence CFD , Fidelity Pointwise

Verification

Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 4 min read
Verification IP , PCIe , pcie gen6 , verification

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis…

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify…

• 8 min read
IDA , Sigrity Aurora , Sigrity Topology Explorer , Power Integrity , SI/PI Analysis , Allegro Package Designer , Signal Integrity , PCB design , Clarity 3D Solver

Breakfast Bytes

Samsung Foundry Roadmap 2022

Recenty, it was the Samsung Foundry Forum (SFF). In fact, there was a pre-event for…

• 4 min read
Samsung , samsung foundry , samsung foundry forum , sff , safe

Computational Fluid Dynamics

Fidelity Pointwise 2022.1 Hot Fix 2 Now Available

Fidelity Pointwise 2022.1 Hot Fix 2 is now available for download and production…

• 1 min read
featured , Pointwise , Computational Fluid Dynamics , fluid dynamics , Mesh Generation , Meshing

Academic Network

Shift-Left Methodology for the Development of Hardware Accelerators Education Kit…

In order to describe the purpose of this education kit , let’s leave the EDA turf…

• 3 min read
virtual prototyping , featured , Education Kit , Tensilica , Stratus , SystemC , high level synthesis , helium

Life at Cadence

Hassle-Free Rigid-Flex PCB Bending EM Analysis

The functionality, safety, and effectiveness of devices using rigid-flex PCBs are…

• 4 min read
rigidflex , electromagnetic

Life at Cadence

Butterfly Network Puts Ultrasound on a Chip with Cadence

About two-thirds of the world’s population lacks access to medical imaging, whether…

• 1 min read
featured , designed with cadence , vision , butterfly network

Breakfast Bytes

2022 Kaufman Award Honors Giovanni De Micheli

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of…

• 5 min read
Kaufman Award , CEDA , IEEE , kaufman hall of fame , esd alliance

Verification

Unraveling PCIe 6.0 FLIT Mode Challenges

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer…

• 6 min read
Verification IP , featured , verification strategy , Functional Verification , VIP , PCIe , pcie gen6 , verification
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