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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
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Blog - Post List

Latest blogs

定制IC芯片设计

Virtuosity: 如何使用ADE Explorer 及ADE Assembler 打开旧版本的ADE 状态和视图文件

您是否发现，当您查看 Virtuoso ® ADE L 状态（State）文件，或者 Virtuoso ® ADE XL 视图 (View) 文件时，默认打开程序仍然是旧版本的…

• 1 min read
Chinese blog , Analog Design Environment , Virtuoso ICADVM18.1 , ICADVM18.1 , ADE Explorer , ADE Migration , maestro , ADE , Virtuoso IC6.1.8 , Virtuoso ADE Explorer , Virtuoso ADE Assembler , IC6.1.8 , ADE Assembler

Breakfast Bytes

Emerging Memories Poised to Explode

A couple of weeks ago was the Persistent Memory Summit. (For more details, see my…

• 5 min read
fram , ReRAM , flash , xpoint , 3D NAND , NAND flash , emerging memories , DRAM , nor flash , MRAM , PCRAM

Breakfast Bytes

DesignCon: Cadence Teaches AMI and IBIS

At the recent DesignCon, Cadence and customer IBM presented a tutorial on Advanced…

• 9 min read
DesignCon , AMI , IBIS , SerDes

PCB、IC封装：设计与仿真分析

2019七大行业动向预测

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “ Breakfast Nibbles: Predictions…

• less than a min read
5G , Chinese blog , 内存 , 无人车 , 3nm , 电动车 , DRAM , 中文 , 汽车 , 云 , 5nm , 神经网络 , AI , EUV

Breakfast Bytes

Sunday Brunch Video for 3rd February 2019

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM:…

• less than a min read
5G , DFT , Memory , CES , modus , mobile , persistent memory , IEDM

Breakfast Bytes

Programming Persistent Memory

I talked earlier this week about the recent persistent memory summit (see my post…

• 5 min read
programming model , persistent memory

Analog/Custom Design

Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

An important requirement for project sign-off is to ensure that all the design simulations…

• 2 min read
verifier , PVT , coverage , Analog Coverage , Analog Simulation , Virtuoso Analog Design Environment , space , Custom IC Design , Assembler , verification

Breakfast Bytes

Persistent Memory

Last week was the latest Persistent Memory Summit. In the semiconductor world, we…

• 8 min read
persistence , Intel , non-volatile , persistent memory summit , ReRAM , optane , MRAM , persistent memory , 3dxpoint

Breakfast Bytes

What Next for Modus DFT?

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the…

• 3 min read
modus , Test , scantest

Verification

Specman is Sweet – Bosch Sensortec's Story

Recently, Bosch Sensortec has been using Specman for their functional verification…

• 1 min read
Specman , Bosch , e , success

Breakfast Bytes

CES: 5G, All Hat and No Cattle

Increasingly, CES seems to be less about consumer electronics, and more about the…

• 9 min read
5G , mmwave , CES , MWC

Analog/Custom Design

Virtuosity: Introducing the Pin Tool

The Pin Tool follows an object-based approach to working with pins by consolidating…

• 2 min read

Life at Cadence

Empowered to Support Our Community

Cadence understands that the success of our business, our employees, and the community…

• 2 min read
Insights on Culture , giving back , Fortune 100 best companies to work for , great place to work

Verification

New Training Bytes Available Now: All About SystemVerilog Classes

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking…

• 2 min read
SystemVerilog , Functional Verification , classes , training , training bytes

Breakfast Bytes

IEDM: Embedded Memories

On the Sunday of IEDM are two short courses, one memory-focused, and one logic-focused…

• 6 min read
Memory , deep learning , eflash , flash , envm , RRAM , MRAM , PCRAM , edram

Breakfast Bytes

Sunday Brunch Video for 27th January 2019

https://youtu.be/1gxIy7TGg3c Made at EBC (camera Sean) Tuesday: DesignCon: The Integrity…

• less than a min read
DesignCon , bletchley park , Amazon , gsa , dan niles

PCB、IC封装：设计与仿真分析

Cadence Sigrity 邀您莅临DesignCon 2019

时间：1月29-31日 地点：Santa Clara Convention Center，美国加州 Cadence诚邀您莅临DesignCon #711 展台，了解如何利用Cadence…

• less than a min read
SI , PI , Chinese blog , 电源完整性 , DesignCon , Multi-Gigabit , IC封装设计 , 光电设计 , 高级封装 , IBIS-AMI , 中文 , SerDes , DDR , Sigrity , 信号完整性

Breakfast Bytes

Amazon Go: Just Walk Out Shopping

Last year you probably heard about Amazon Go when it opened in Seattle. This is a…

• 3 min read
amazon go , mobile , Amazon , whole foods

Analog/Custom Design

Spectre Tech Tips: Optimizing Spectre APS Performance

This blog discusses how to optimize the Spectre APS performance for analog and mixed…

• 14 min read
spectre aps , Circuit simulation , ADE Explorer , simulation performance , Simulation Accuracy , Spectre XPS MS , ADE , Spectre Tech Tips , Spectre
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