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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF Engineering

μWaveRiders: RF/Microwave Technology Driving the Connected Car

A recently published white paper, RF/Microwave Technology Driving the Connected Car…

• 2 min read
AWR Design Environment , RF communications , RF design , Radar systems , ADAS , Cadence Intelligent System Design

System, PCB, & Package Design 

ASCENT: Some Basic Rules for Design Verification

In part 1 of this blog post, we covered the model-less aspect of Allegro® System…

• 2 min read
17.4 , system reliability , design verification , 17.4-2019 , PCB design , Allegro System Capture , ASCENT , simulation , Schematic

Breakfast Bytes

Allegro X, the Design Platform for the Next Generation of Intelligent System Des…

allegro x system design and pcb design with machine learning and unparalleled pr…

• 2 min read
PCB , machine learning , PCB design , pcb machine learning , allegro x

PCB設計／ICパッケージ設計

ASCENT: Unified Searchを使って最適な部品を見つける

デザインに適した部品を見つけることは、設計作業の中で最も時間がかかるパートだと言う人もいます。もしそうであるならば、必要なものをすばやく見つけるのに有効な、あらゆる援助を利用することが求められます…

• less than a min read
17.4-2019 , Allegro System Capture , japanese blog , Unified Search , ASCENT , Schematic , Allegro

Digital Design

A Proven Way to Simulate High-Frequency Electro-Magnetic Effects Using Quantus Extraction…

Cadence offers multiple electromagnetic (EM) extraction technologies to model the…

• 3 min read
Extraction , quantus rlck , Quantus

Breakfast Bytes

TSMC's 3DFabric

I already wrote about TSMC's advanced-node roadmap in my post TSMC: Advanced Technology…

• 3 min read
CoWoS , packaging , TSMC , TSMC Technology Symposium , InFO , 3dfabric

Computational Fluid Dynamics

This Week in CFD

I hope you didn't think I had forgotten. But last Friday was a tad busy so I didn…

• 1 min read
CFD , Aerospace , Pointwise , Computational Fluid Dynamics , fluid dynamics , CFD Applications , NUMECA , CAE , Mesh Generation , Meshing

Spotlight Taiwan

超大規模資料中心、行動通訊與汽車 推動先進製程節點不斷創新 - 摩爾定律仍加速前行!

原文作者: Cadence資深副總裁暨數位與簽核事業群總經理滕晉慶(Chin-Chi Teng) 原文出處: https://www.linkedin.com/posts…

• less than a min read
3nm , Hyperscalers , Digital Implementation , taiwanese blog

Breakfast Bytes

Hardware Hacking Party Tricks

Toward the end of April, Black Hat ran a webinar Hacking Party Tricks: Techniques…

• 6 min read
security , glitching , blackhat , JTAG

Verification

Webinar: Using e Reflection

Join Cadence Training and Software Architect Efrat Shneydor for this free technical…

• 1 min read
Specman , Specman e , training , webinar , reflection

Breakfast Bytes

Sunday Brunch Video for 6th June 2021

https://youtu.be/sqEzhpQZmbo Made on my dining table (camera me) Monday: Memorial…

• less than a min read
sunday brunch

Breakfast Bytes

A Year of Breakfasts 2021

This year's Breakfast Bytes annual is out. It is titled A Year of Breakfasts 2021…

• 1 min read
a year of breakfasts 2021 , breakfast bytes book , Breakfast Bytes

Computational Fluid Dynamics

Pointwise V18.4 R4 Now Available for Download and Production Use

As the title says, Pointwise Version 18.4 R4 is now available for download and production…

• 1 min read
CFD , Pointwise , Computational Fluid Dynamics , Mesh Generation , Meshing

Analog/Custom Design

Start Your Engines: Modeling Current-Based Port Connections between Electrical and…

In a mixed-signal simulation, the electrical signal modules and real number modeling…

• 5 min read
R2E conversion , real number modeling , AMS , AMS Designer , Start Your Engines , E2R , Mixed-Signal , mixed-signal verification

Breakfast Bytes

TSMC: Advanced Technology for Smartphone and HPC Platforms

Yujun Li, TSMC's director of business development for high-performance computing…

• 3 min read
5G , n5 , n5hpc , n3 , TSMC , HPC , n7 , n7hpc

定制IC芯片设计

Virtuoso Meets Maxwell: 从系统的角度思考—— 行业领先的IC与IC封装设计/验证工具间互操作性的优势

当下大多数的模拟，射频和混合信号设计都要求在不同衬底工艺上集成多颗IC，以达到所需的性能。异构元件集成方法可以帮助设计师实现单片SoC不容易实现的设计结果。与此同时…

• less than a min read
Chinese blog , IC Packaging , Virtuoso Meets Maxwell , Virtuoso RF Solution , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Spectre , Allegro

System, PCB, & Package Design 

BoardSurfers: Voiding Text in Copper Shapes

Almost every PCB design includes different types of shapes, mainly for ground and…

• 3 min read
PCB , 17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

CEO Outlook: "Let's Take Advantage of Our Industry Being in the Spotlight"

The Electronic System Design Alliance CEO Outlook took place on May 16. Bob Smith…

• 13 min read
ESDA , semi , ceo outlook , esd alliance

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: Clarity 3Dソルバーでのシミュレーション用にポートを設定する

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Virtuoso Meets Maxwell , Virtuoso RF Solution , Electromagnetic analysis , ICADVM20.1 , japanese blog , Clarity 3D Solver , Custom IC Design , Virtuoso Layout Suite EXL
CDNS - Fix Layout Hompage