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Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education…

Corporate
• 6 min read
news story , featured , Cadence Academic Network , SKY130

Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

IC Packagers: Analyzing and Fixing Wire Bond-Specific Design Issues

Design reuse is the key to faster design cycles in today’s packaging design industry…

• 3 min read
17.4 , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , wirebonding

Computational Fluid Dynamics

Tutorial Tuesday - It's Time to Learn Some Meshing

Today's not just Tuesday, it's Tutorial Tuesday. What's that, you ask? Each Tuesday…

• less than a min read
CFD , video , Pointwise , tutorial , Computational Fluid Dynamics , Mesh Generation , Meshing

Breakfast Bytes

Rapid Adoption Kits for Arm's Premium Mobile Platforms

Today, Arm announced its new lineup of processors for mobile. These are the first…

• 4 min read
Rapid Adoption Kit , RAK , digital full flow , mobile , verification full flow , ARM

System, PCB, & Package Design 

BoardSurfers: Managing Minor Spacing DRCs Using Manufacturing Tolerances

While translating boards from different PCB design applications or changing design…

• 2 min read
17.4 , BoardSurfers , EDA , PCB Editor , 17.4-2019 , Allegro PCB Editor , Allegro

SoC and IP

Introducing Cadence IP for PCIe 6.0

Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous…

• 3 min read
controller IP , CXL , Design IP , IP , PHY , PCIe , semiconductor IP , SerDes , PCIe 6.0 , PCI Express

Breakfast Bytes

PCIe 5.0 and 112G-LR IP in TSMC N5

Well, that's a lot of tech gobbledegook in the title of this post. Here's what it…

• 3 min read
pcie version 5 , 112G-LR , PCIe , 112g , SerDes , PCI , PCI Express

Computational Fluid Dynamics

This Week in CFD

This week’s CFD news includes both an image of the week and an application of the…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics , fluid dynamics

Breakfast Bytes

Linley: Habana and Cerebras

In the recent Linley Spring Processor Conference, there were many processors for…

• 4 min read
linley processor conference , cerebras , Linley , aws , gaudi , AI , habana

カスタムIC／ミックスシグナル

Spectre FX: FはFastのF、本当に高速

本日5月20日(米国時間)、ケイデンスは、最大で3倍の速度（同等以上の精度で）を持つ次世代FastSPICE回路シミュレータSpectre FX Simulatorを発表しました…

• less than a min read
Circuit simulation , FastSPICE , Spectre , spectre fx , japanese blog , SPICE

Spotlight Taiwan

增強系統分析與PCB設計研發戰力 - 隨選影片 向您致敬!

PCB設計暨系統分析 - 強檔精彩影片回顧! 5G、AI、工業物聯網（IIoT）、自駕車和超大規模（hyperscale）運算等技術的匯聚，為半導體產業帶來了新商機…

• less than a min read
PCB , Chinese blog , celsius , Sigrity X , taiwanese blog , Allegro , clarity

Breakfast Bytes

Spectre FX: F Is for Fast, Really Fast

Today, Cadence announced the Spectre FX Simulator, a next-generation FastSPICE circuit…

• 5 min read
Circuit simulation , FastSPICE , Spectre , spectre fx , SPICE

Life at Cadence

Moore’s Law Is Still Accelerating

Moore’s Law Is Still Accelerating. I’m looking at Moore’s Law differently, measuring…

• 4 min read
process , Advanced Node , implementation , moore's law

Breakfast Bytes

RSAC: Opening Keynote and a Whitrospective

The RSA Conference on cybersecurity took place in the middle of May. This year, the…

• 5 min read
rsac 2021 , diffie , rsa conference , rsa , rsac

中文技术专区

视频演示：PCIe 5.0设计究竟应该怎么做

原文链接： https://community.cadence.com/cadence_blogs_8/b/ip/posts/taking-the-wraps-off…

• less than a min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , SerDes , Compute Express Link

Spotlight Taiwan

淺談運算流體力學(CFD)與Pointwise公司

原文出處: Please Excuse the Mesh: CFD and Pointwise 作者: Paul McLellan Cadence於今年四月收購了流體動力學公司Pointwise…

• less than a min read
CFD , Pointwise , taiwanese blog

System, PCB, & Package Design 

ASCENT: Analyzing Electrical Stress, Aging, and Faults of PCB Components

Component heating, Joule heating, heat sinks…does the very idea of checking the stress…

• 2 min read
System Capture , Cadence Design Systems , 17.4 , system reliability , logical design , design integrity , logic capture , 17.4-2019 , PCB design , device reliability , Allegro System Capture , Derating , ASCENT , electrical stress analysis , Schematic , Allegro

Verification

How to Verify LPDDR5 from IP to System Level?

LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs…

• 3 min read
Verification IP , SoC verification , Specman , Memory , Functional Verification , VIP , JEDEC , Memory Model Portfolio , storage , lpddr5 , lpddr5x

Breakfast Bytes

Vietnamese Orphanages and Smartphone Apps

Kids in orphanages have a hard life. You only have to read Oliver Twist to get some…

• 6 min read
technovation , team4tech , kidspire vietnam

Analog/Custom Design

Virtuoso Meets Maxwell: Making the Ports Ready for Simulations in Clarity 3D Sol…

This blog describes the features in Virtuoso Layout EXL and Clarity 3D Solver that…

• 6 min read
Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , ICADVM20.1 , Clarity 3D Solver , Custom IC Design , Virtuoso Layout Suite EXL
CDNS - Fix Layout Hompage