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Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
Reela Samuel 2 Sep 2025 • 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

  • All 6048
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  • System, PCB, & Package Design  982
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Blog - Post List

Latest blogs

Breakfast Bytes

Ericsson Cellular Network at TÜV Rheinland Test Center

At the end of March, I went to the TÜV Rheinland Test Center. TÜV stands for Technischer…

Paul McLellan 8 Apr 2022 • 4 min read
Automotive , Ericsson , tüv , mobile

Breakfast Bytes

Identity Is the New Perimeter

On March 10th, Black Hat organized a webinar called Identity is the New Perimeter…

Paul McLellan 7 Apr 2022 • 9 min read
security , black hat , orange

Analog/Custom Design

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 13: Analog Fault S…

While the analog and mixed-signal components are the leading source of test escapes…

Parula 7 Apr 2022 • 4 min read
Automotive , legato , ICADVM20 , functional safety , analog fault simulation , analog , training bytes , Virtuoso , Analog IC Design videos , Spectre , 1 , Virtuoso Video Diary , aging , Custom IC Design , IC6.1.8 , reliability , Legato Reliability , ADE Assembler

PCB設計/ICパッケージ設計

2022年3月リリース、Cadence OrCAD / Allegro17.4-2019 HotFix SPB17.40.028の新機能ハイライト

OrCAD® および Allegro®のHotFix 028 (QIR 4, アプリケーションのスプラッシュ画面で は “2022” と表示されます) の更新プログラムが…

SPB Japan 6 Apr 2022 • less than a min read
17.4 , PCB Editor , 17.4-2019 , OrCAD , Allegro System Capture , japanese blog , Allegro PCB Editor , Pulse , Allegro

Breakfast Bytes

Sam Zeloof: Who Needs a Cleanroom When You Have a Garage?

At the end of last year, I was mindlessly looking at YouTube when their "algorithm…

Paul McLellan 6 Apr 2022 • 3 min read
sam zeloof , garage

Computational Fluid Dynamics

Replicating da Vinci’s Aerial Vehicle Design

The increasing value of the drone industry is pushing the limits of evaluating and…

Veena Parthan 6 Apr 2022 • 3 min read
vehicle design , Unmanned Aerial Vehicles , UAV , da Vinci , CFD Applications , engineering , extreme maneuvers , drones , simulation , Aerodynamics

Computational Fluid Dynamics

Rank-N Nonlinear Harmonic Method Unlocks More Precise And Reliable Turbomachinery…

The NLH Rank-n feature unlocks the possibility of simulating unsteady phenomena across…

AnneMarie CFD 5 Apr 2022 • 1 min read
CFD , turbomachinery , webinars , Computational Fluid Dynamics , fluid dynamics , nonlinear harmonic , CFD Applications , simulation software , rank-n , nlh , Turbo , simulation

Breakfast Bytes

Jack Dongarra Receives Turing Award

Last week, the ACM announced that Jack Dongarra was being honored with the 2021 Turing…

Paul McLellan 5 Apr 2022 • 4 min read
turing award , supercomputer

SoC and IP

TWS Earbud Design: Scaling up

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier…

The Prakashian 4 Apr 2022 • 9 min read
Tensilica DSPs , Tensilica

SoC and IP

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

The Prakashian 4 Apr 2022 • 5 min read
featured , Tensilica

Verification

LPDDR5 Verification from PHY to System Level

LPDDR5 DRAM aims to serve a wide array of markets and plays a vital role in the system…

Vinod Khera 4 Apr 2022 • 6 min read

Breakfast Bytes

Intelligent System Analog Design

There are many perceptions about analog design that might have been true once. For…

Paul McLellan 4 Apr 2022 • 6 min read
analog , Virtuoso , mixed signal , Virtuoso Layout Suite EXL

PCB設計/ICパッケージ設計

BoardSurfers: Allegro PCB Editorでの寸法データ入力に関する概要

プリント基板がより複雑かつ軽量になっていく中、費用対効果が高く信頼性の高い基板の設計・製造は、これまで以上に重要となっています。デザインの詳細情報が不正確/不完全では…

SPB Japan 3 Apr 2022 • less than a min read
17.4 , BoardSurfers , manufacturing , japanese blog , Allegro PCB Editor , Allegro

Computational Fluid Dynamics

Combining Structured and Unstructured Meshes: The Holy Grail for CFD Engineers

Flow solvers must be able to read the type of meshes behind them, and as most flow…

AnneMarie CFD 1 Apr 2022 • 4 min read
CFD , Automated meshing , mesh , structured grids , Computational Fluid Dynamics , fluid dynamics , structured meshing , CFD Applications , unstructured meshing , simulation software , Meshing , simulation , unstructured grids

Breakfast Bytes

The All-Purpose EDA Keynote

Today, it is April 1st and so it is tempting to do some spoof post, but most of those…

Paul McLellan 1 Apr 2022 • 5 min read
edagraffiti , Blogging , parody , keynote

Life at Cadence

Celebrating Women's History Month with Girl Geek X!

To celebrate Women’s History Month in March, Cadence partnered with Girl Geek X for…

Mary Kasik 31 Mar 2022 • 1 min read
inclusion , Women at Cadence , women , Women's History Month , girl geek , diversity , Women in Technology

Breakfast Bytes

DVCon: There Be Dragons!

At the recent DVCon, there was a panel session titled SoC Verification Hidden Dragons…

Paul McLellan 31 Mar 2022 • 12 min read
formal , Emulation , DVcon , simulation , verification

System, PCB, & Package Design 

Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.028 is Now Available

The HotFix 028 (QIR4, indicated as 2022 in the application splash screens) update…

AllegroReleaseTeam 31 Mar 2022 • 6 min read
Cadence Design Systems , 17.4 , PSpiceA/D , PSPICE , PCB Editor , 17.4-2019 , OrCAD , PCB design , Allegro System Capture , Pulse , Allegro

Analog/Custom Design

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator

DSPF files are an integral part of post-layout simulations. This blog introduces…

Stefan Wuensche 31 Mar 2022 • 5 min read
spectre aps , post-layout simulation , EMIR Analysis , EMIR Simulation , DSPF , netlist , Spectre , Spectre X Simulator , EMIR
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CDNS - Fix Layout Hompage

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