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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Life at Cadence

Restoring Nature, One Vine at a Time

Written by Shrini Farrahi A dedicated team of 30 Cadence volunteers recently came…

• 1 min read
Cadence Giving Foundation , giving back , LifeAtCadence , We Are Cadence , volunteering , One Cadence One Team

System, PCB, & Package Design 

Case Study: How to Sign Off Your UCIe Interface

As 3D heterogeneous integration (3DHI) systems increase in complexity, the importance…

• 3 min read
IC Packaging , Signal Integrity , Sigrity , SystemSI

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Power Tradeoffs for Chiplets: What Designers Need to Know

The rise of chiplets in advanced system design presents opportunities as well as…

• 3 min read
chiplets , Voltus IC Power Integrity Solution , Power Integrity

Corporate News

Unlocking Breakthroughs with Accelerated Compute

The future of system and electronic design is here—and it’s unprecedentedly fast…

• 6 min read
Protium , Palladium , accelerated compute , millennium

Verification

Evolution of CXL PBR Switch in the CXL Fabric

Compute Express Link (CXL) is a transformative technology that significantly improves…

• 5 min read
Fabric manager , Routing , switch , CXL3.0 , CXL switch , TYPE , SPID , PBR , DPID

Life at Cadence

Shaping the Future Through Experience

This summer, Cadence hosted five interns in partnership with Break Through Tech at…

• 2 min read
STEM , Work that matters , LifeAtCadence

SoC and IP

CNNs and Transformers: Decoding the Titans of AI

In the rapidly advancing field of artificial intelligence, two neural network architectures…

• 8 min read
IP , ip cores , Tensilica , SSG , semiconductor IP , AI

SoC and IP

From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success

Data rates are escalating with seemingly no end in sight due to the insatiable demand…

• 2 min read
DIP , ip validation , post silicon , full subsystem , verification

Corporate News

Alphawave Semi – Designing High-Speed Connectivity Solutions with Cadence Tools

Alphawave Semi designs high-speed connectivity solutions for customers in high-growth…

• 1 min read
celsius , designed with cadence , Sigrity , connectivity , clarity

Life at Cadence

Employee Spotlight: Engineering Excellence and Team Spirit at Cadence

Behind every milestone at Cadence is a team of passionate individuals who bring energy…

• 1 min read
Cadence Culture , LifeAtCadence

Verification

UEC-CBFC: Credit-Based Flow Control for Next-Gen Ethernet in AI and HPC

For ages, Ethernet has been the backbone of networking — starting from simple web…

• 2 min read
Verification IP , artificial intelligence , Ethernet VIP , Functional Verification , VIP , UEC , machine learning , Ethernet , Hyperscalers

Digital Design

Clock Tree Synthesis (CTS): The Backbone of Physical Design

In the intricate world of digital design, timing is everything. At the heart of this…

• 4 min read
EDI , online courses , HT Algorithme , STA , Cadence Online Support , training , Logic Design , training bytes , clock tree synthesis , Digital Implementation , Innovus , SDC , skew , online training , clock gating

Digital Design

EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security…

• 4 min read
videos , online courses , Electronic Design Automation , training bytes , Semiconductor , online training

Life at Cadence

Uniting Innovators: CIC 2025 Showcases Cadence’s One Team Culture

What happens when 500 Cadence employees from 22 countries come together to share…

• 6 min read
innovation , Cadence Culture

Verification

Training Insight: Unlocking the Power of the Xcelium Logic Simulator

In the fast-paced world of digital design and verification, simulation tools are…

• 1 min read
Xcelium Logic Simulator , Training Insights

Analog/Custom Design

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer , Spectre , Spectre Fast Monte Carlo , Spectre X Simulator

Verification

Fast Emulation Requires Fast Debug! This Is How It is Done

Introduction Emulation has become a critical tool for verifying complex system-on…

• 3 min read
debug , Palladium , verisium , Emulation , Verisium Debug

Verification

Scalable I/O Virtualization: A Deep Dive into PCIe’s Next Gen Virtualization

The demands of modern cloud computing—massive scale, constant agility, and tight…

• 6 min read
Verification IP , Functional Verification , VIP , PCIe
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